Methods and apparatus for translating incompatible bus transactions

DETAILED DESCRIPTION Circuit arrangements and methods are disclosed for upgrading an 040-based personal computer system using an optional, peripheral add-in card.
In one embodiment, the present invention comprises a PowerPC-based microprocessor, such as the MPC601, having one megabyte of on-board direct mapped level 2 external cache memory arranged as tag and data blocks.
The PowerPC-based board is inserted into a processor-direct data path sharing the data and address bus with the 040 microprocessor.
System random access memory (RAM), I/O, and other functional blocks are present on the main board comprising the 040-based computer.
The MPC601 is coupled via an address bus to the tag cache, which is conventionally organized to have address bits and one valid bit for each entry.
The MPC601 is further coupled via a data bus to a bus translation unit (BTU), a read only memory (ROM) storing the operating system code for the PowerPC microprocessor, the data cache, a dual frequency clock buffer, and other interface components such as a processor-direct data path including address and data latches.
The on-board address and data buses are clocked at half the frequency of the PowerPC microprocessor.
When the computer is turned on, the valid bits of the on-board level 2 cache are reset to zero by setting a cache invalidate bit in a register within the BTU, thereby causing the BTU coupled to the data bus to gain control of the PowerPC address bus and thereafter sequentially clearing all valid bits in the tag cache.
After the cache has been cleared, the cache can be enabled by setting an appropriate register within the BTU, whereafter a memory map for the PowerPC MPC601 is enabled.
Cache entries are made during a burst read by the MPC601 when a cache inhibit pin is inactive, and may be made from ROM, RAM, or from any other cacheable space.
Once filled and running, any updates written to the on-board cache will write-through to the system DRAM.
The 040 processor on the main board is disabled after power-up by using the 040 JTAG test port after inactivating the power-on fast reset