Microcoded microprocessor with shared ram

DETAILED DESCRIPTION The present invention is a system for utilizing a single RAM array as a control store for microcode, and as a memory for other functions such as, for example, memory cache, page table cache, and scratch pad.
The single shared DATA/ADR bus reduces the number of I/O connections that must be designed into the processor and facilitates overall reduction of hardware.
In a preferred embodiment, selected microinstructions are stored in a ROM included on the processor.
A ROM accessing system accesses a required microinstruction from the ROM for execution during a given clock cycle when the shared RAM array is performing some other function.
Thus, the execution of the microprogram is not interrupted when the shared RAM is busy, thereby increasing the operating speed of the processor.
In an alternate embodiment, provision for generating a no-op signal is included to stop execution of the microprogram when the shared RAM array is performing some other RAM function.
This embodiment is structurally simple, but may take longer to execute a microprogram than the embodiment including the onboard ROM.
According to a further aspect of the invention, each microinstruction, for use in the embodiment having onboard ROM, includes a control field for determining whether the next microinstruction is accessed from the shared RAM array or the onboard ROM and a link field for specifying the address in the ROM of the next microinstruction to be accessed from the onboard ROM.
Other features and advantages of the invention will be apparent in view of the drawings and the following detailed description.