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Microcomputer system for communication
| Details |
Inventors: Okochi, Toshio; Miyazaki, Takeshi;
Assignee: Hitachi, Ltd. (Tokyo, JP)
Primary Examiner: Shaw; Gareth D.
Assistant Examiner: Kulik; Paul
Attorney, Agent or Firm: Fay, Sharpe, Beall, Fagan, Minnich & McKee
A microcomputer system comprising a central processor unit, communication apparatus having a first memory to store receipt data, data transfer controller to transfer the receipt data stored in the first memory, a second memory, and counting apparatus, wherein the receipt data consists of at least one unit information item, and the counting apparatus is caused to count up in accordance with a number of the unit information items. |
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DETAILED DESCRIPTION In view of the aforementioned drawback, the inventors studied a system according to which, in the case where the frames are sent in somewhat successively as described above, priority is given to the transfer of the frames received in the FIFO to the memory.
That is, at the first stage, all the frames which are successively sent in are received and transferred to the memory MEM.
At the next stage, an interrupt is applied from, e.
g.
, the DMA controller to the microprocessor, whereby the microprocessor becomes a bus master in place of the DMA controller and executes the processes for the frames transferred to the memory MEM.
Since the prior-art system does not include the function of counting the number of received frames, the number of frames to be processed by the microprocessor after the end of the transfer of the frames to the memory MEM is not known.
In this regard, the inventors' study has revealed that normal analyses might fail to progress because the length of an interrupt request signal or the number of interrupt request signals which, e.
g.
, the DMA controller ought to send to the microprocessor is unknown.
Certainly the number of frames can be known in such a way that the microprocessor reads out all the received data items in the memory MEM after the end of the transfer.
With such a method, however, a considerably long time is expended merely on the procedure for knowing the number of frames.
An object of this invention consists, in a microcomputer system having a serial communication device which transmits data in frame unit, in reducing an overhead in the reception of data thereby to raise the efficiency of communication and also lightening the burden of a microprocessor thereby to improve the throughput of the system.
The aforementioned and other objects and novel features of this invention will become apparent from the description of the specification as well as the accompanying drawings.
A typical aspect of performance of this invention is summarized as follows: In a case where frames are being received somewhat successively, data transfer to a memory is preferred, and a microprocessor is inhibited from becoming a bus master
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I/O Systems 
