Microcomputer with automatic refresh of on-chip dynamic RAM transparent to CPU

DETAILED DESCRIPTION In accordance with one embodiment of the invention, a microcomputer device is disclosed containing a ROM for program memory, a read/write memory, and a CPU in a single integrated circuit.
Input/output ports, interrupt and operating mode controls are memory mapped in the same logical address space as the program and read/write memory.
The read/write memory is an array of one-transistor type dynamic storage cells in which data bits are stored in capacitor; refresh of this dynamic RAM is accomplished in a manner transparent to the CPU by an automatically-incremented address counter.
Each data bit uses two one-transistor cells in a balanced, complementary array.
This construction allows the read/write memory to be much more dense compared to the traditional six-transistor static RAM cells used in microcomputers, and yet provides favorable noise margins and avoids refresh overhead.
The use of two cells for each bit rather than the conventional dummy cell arrangement provides a larger voltage differential for the sense amplifier and thus provides more reliable sensing; because of the layout of the bar, the array is partitioned such that multiple rows of dummy cells would be needed if the conventional dynamic RAM structure was used, and so the increase in the number of cells is less than the factor of two which would be initially expected.
The two complementary cells also allow the one-level to decay further and still be reliably sensed, so the refresh time can be longer; this allows the system clock to be slower, and permits fewer constraints on writing ROM programs because a longer time period can be tolerated between refresh for a given row.
The RAM is refreshed by a row address applied from a refresh counter on every cycle that the RAM is not accessed, plus the first state of every long memory reference; a program with intensive multiply or divide loops making repeated access to the register file with few long memory cycles would conceivably leave long periods of few refresh cycles, so longer refresh time is needed