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Microprocessor-with-pipeline-system-having-exception-processing-features

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Details

Inventors: Ohtsuka, Akira; Shimizu, Toru;
Assignee: Mitsubishi Denki Kabushiki Kaisha (Tokyo, JP)
Primary Examiner: Ray; Gopal C.
Assistant Examiner:
Attorney, Agent or Firm: Townsend and Townsend Khourie and Crew

A method and apparatus for processing exceptions in a microprocessor having a plurality of pipelined stages. The method comprises the steps of generating an exception processing code at a given stage to indicate the occurrence of an exception at the given stage; temporarily stopping processing at the given stage; transferring the exception processing code to a special stage; decoding said exception processing code at the special stage; and causing the pipeline to execute exception processing when the exception processing code is decoded at the special stage. Using the invention, the microprocessor can avoid much of the delay and complexity resulting from using an external circuit to control exception processing and can cope with the occurrence of an exception at any stage without prematurely cancelling or reexecuting processing steps. The invention is simplified in both hardware and software, and can easily cope with expansion of the number of stages.

DETAILED DESCRIPTION In the light of the above problems, the present invention has been designed.
A first object of this invention is to provide a microprocessor having a pipeline system which can cope with generation of exceptions at any stage of the pipeline.
Yet another object of the invention is to provide a processor which performs exception processing without using an elaborate external control circuit.
Still another object of the invention is to provide a processor which performs exception processing without unnecessarily cancelling or reexecuting previously performed processing.
Another object of this invention is to provide a microprocessor capable of easily coping, in a hardware and software manner, with variations in the number of stages of the pipeline.
Another object of this invention is to provide a processor which performs exception processing while having pipelining for both calculation and instruction processing.
According to the invention, there is provided for a processor of the type having a pipeline formed by a plurality of consecutive stages, a method for processing exceptions which includes the step of generating an exception processing code at a given stage to indicate the occurrence of an exception at the given stage, the kind of exception, and the identity of the given stage.
Thereafter, processing is temporarily stopped at the given stage and the exception processing code is transferred to and decoded at a special stage which causes the pipeline to execute exception processing.
In a preferred embodiment, the exception processing codes are transferred from and received at each stage in the pipeline using a plurality of D flip-flops.
The exception processing code is decoded at the special stage using a logic array consisting of NAND gates, inverters, and D flip-flops.
The above and further objects and features of the invention will more fully be apparent from the following detailed description with accompanying drawings.

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