 Ejection mechanism |
| In its first preferred embodiment, the present invention comprises a housing for up to two cards ... |
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| Computer system having a structure for easy assembling/disassembling of peripheral equipment |
| Accordingly, it is an object of the present invention to provide an improved portable computer. It ... |
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| Media eject mechanism |
| It has been discovered that a media eject mechanism which includes an L shaped eject member having ... |
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| Media module locking and ejecting mechanism |
| In accordance with the present invention, an apparatus for locking and ejecting a media module in a ... |
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| Device for mounting fan in a portable computer |
| Accordingly, it is an object of the present invention to provide an improved device for mounting a ... |
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| Personal digital assistant and associated computer host device bay structure |
| In carrying out principles of the present invention, in accordance with a preferred embodiment ... |
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| Portable computer having latching hooks |
| In one embodiment, as shown in FIG. 1, computer system 10 includes a microprocessor 12, which is ... |
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| Data set network diagnostic system |
| FIG. 1 depicts a communication system, or network, in which the present invention is used. In ... |
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| Recording medium of flat surface with resin filled ring grove |
| Accordingly, a general object of the present invention is to provide a disc and a manufacturing ... |
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| Analog subscriber carrier system repeater with automatic gain and slope correction |
| OF THE INVENTION Referring now to FIG. 1 a subscriber carrier terminal at central office 2 is ... |
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Missing clock detection circuit
| Details |
Inventors: Takii, Tomio;
Assignee: NCR Corporation (Dayton, OH)
Primary Examiner: Zache; Raulfe B.
Assistant Examiner:
Attorney, Agent or Firm: Cavender; J. T., Hawk, Jr.; Wilbert, Morris; Jeffrey P.
A circuit for detecting digital data recorded on a magnetic recording medium is disclosed wherein data is detected by detecting a missing clock and fixed data at the missing clock location. Clock and data pulses are interleaved on the recording medium and encoded to distinguish data and detecting the missing clock by encoding data corresponding to signal absence into the bit position adjacent to the last bit of the missed clock bit when such condition is present. The clock and data bits are detected from the decoded signal read from the recording medium by timing the first period between succeeding bits which is of greater time duration than the interval between succeeding clock and data bits but shorter than the interval between succeeding clock bits having a data bit interposed therebetween. A second timing means times the second period which is of greater time duration than the interval between two succeeding clock bits but shorter than the interval between a clock and data bit adjacent to the next clock bit. The times are then compared to determine whether a missing clock has occurred and a correction code is generated. |
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DETAILED DESCRIPTION Missing clock pulses are detected in accordance with the present invention by a detection circuit for reading encoded data including a timer for measuring a first time or period which is of greater duration than the period between a clock bit and a succeeding data bit, but of less duration than the period between two succeeding clock bits having a data bit interposed therebetween; and after which period the timer is stopped.
A second timer measures a second period which is of greater duration than the period between two succeeding clock bits but shorter than the period between a clock bit and a data bit which appears after the next clock bit, at the conclusion of which second period the second timer is stopped.
In the normal state, i.
e.
, when no clock signal is missing, the first timer continuously measures the time period as each clock pulse is received.
When a signal is received within the first period after detection of a clock pulse, the signal is decoded as a data signal.
Conversely, when a signal is received after the conclusion of the first measured period after the decoding of a clock pulse, the signal is decoded as a clock signal.
In this manner, clock and data pulses are separated.
The second timer continuously measures the period between detected clock signals.
A missing clock is considered detected when, after detection of a first clock pulse, the next clock pulse is not detected within the second period.
Upon this occurrence, and when a data bit signal indicative of a digital "one" is detected after the missing of one or more succeeding clock pulses, the data bit signal is decoded as a clock signal, as it has been decoded following the conclusion of the first time period after the detection of the clock signal and immediately preceding the missing of a clock pulse.
Thus, a "false" decoding of clock and data signals is caused to occur.
However, this false decoding is corrected when a new clock pulse is detected immediately following the period during which the clock pulse is missing
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I/O Systems 
