Multiple mode memory module

DETAILED DESCRIPTION OF THE INVENTION Referring first to FIG.
1 there is shown in block diagram form a portion of an information processing system 10.
System 10 includes a system bus 12 which couples together a number of bus connections including a memory control unit (MCU) 14.
Other bus connections, such as a CPU (not shown) provide data to the MCU 14 to be written to memory and also receive data read from memory.
Coupled to MCU 14 via a memory bus (MEMBUS) 16 are one or more memory units (MUs) 18.
For example, in the illustrated embodiment up to eight MUs 18 (MU0-MU7) can be coupled to the MCU 14 via the MEMBUS 16.
MEMBUS 16 can be seen to comprise two groups of signal lines including a control bus 20 and a data/address bus 22.
Referring to FIG.
2a there is shown the memory bus 16 in greater detail.
The control bus 20 can be seen to comprise a plurality of signal lines which are sourced by, for example, a memory interface state machine 24 on the MCU 14.
The memory interface state machine 24 is responsive to a memory access type opcode which is generated by a bus connection and which is sent over the system bus 12 to the MCU 14.
The opcode defines a particular type of memory access such as a double-word read, a quad-word read, or a word or double-word write.
The memory interface state machine 24 decodes the opcode and provides the necessary sequence of control signals to the MUs 18.
A control and timing logic block 26 on the MU 18 receives the control bus 20 signals and, in synchronism with a memory clock (MEMCLK), generates a plurality of internal timing signals for the MU 18.
The MU 18 can be further seen to include an odd double-word memory plane 28 and an even double-word memory plane 30.
Planes 28 and 30 are each comprised of a plurality of memory devices which are preferably DRAMS.
In the illustrated embodiment each of the planes 28 and 30 is differentiated into an upper and a lower half, each half having eight megabytes of storage organized as one megabyte by 78 bits.
Sixty-four of the bits comprise a data double-word and the remaining 14 bits are error detection and correction (ECC) syndrome bits