Multiplexed and interlaced charge-coupled serial-parallel-serial memory device

DETAILED DESCRIPTION Referring first to FIGS.
1 to 6 inclusive, there is shown the scrambled data bit effect produced by conventional interlaced serial-parallel-serial configurations in accordance with the prior art, in order to illustrate the problem obviated by the present invention.
In each of these figures the serial input register section is indicated at S and the parallel section is indicated at P.
Only the first two rows of the parallel section P are shown.
For simplicity and clarity in illustration, the serial input section S is shown as having only eight charge packet storage sites, and the parallel section is shown as having only eight columns each associated with a respective one of the serial section sites.
It will be understood that in a production embodiment both sections may have many more sites and columns, respectively.
Referring to FIG.
1, the first four data bits of a serial bit stream are designated 1 to 4 respectively and are shifted serially into the serial input section S as shown.
Each bit is transferred to the first storage site by the input clock signal .
phi.
1.
The serial transfer of the charge packets corresponding to the respective bits is achieved by conventional clock signals .
phi.
A and .
phi.
B.
It will be understood that the clock signals .
phi.
A, .
phi.
B, .
phi.
1, .
phi.
1', .
phi.
2' shown in FIG.
1 are also operative in FIGS.
2 to 6 inclusive, although not shown to avoid unnecessary duplication.
As viewed in FIG.
2, the clock signal .
phi.
2' causes the four charge packets corresponding to the first four data bits 1, 2, 3, 4 to be transferred simultaneously in parallel into the first row of the parallel section P.
It will be seen that the charge packets corresponding to the first four data bits occupy alternate charge storage sites in the first row of the parallel section P.
Referring now to FIG.
3, the first four data bits 1, 2, 3, 4 have been transferred by clock signal .
phi.
1' into the second row of the parallel section P while the charge packet corresponding to the fifth data bit designated at 5 has been shifted into the first charge storage site of the serial input section S