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| Arbitration circuitry for deciding access requests from a multiplicity of components |
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Multiprocessor systems having distributed shared resources and deadlock prevention
| Details |
Inventors: Bagnoli, Carlo; Perrella, Guido; Majo, Tommaso;
Assignee: Honeywell Bull Italia S.p.A. (Caluso, IT)
Primary Examiner: Clark; David L.
Assistant Examiner: Loomis; John C.
Attorney, Agent or Firm: Phillips; J. H., Solakian; J. S.
In a data processing multiprocessor system having distributed shared resources where each system processor (7) is provided with at least a local memory (8) to which it get access through a local bus (11), and with an interface unit (10) for connection of the local bus (11) to a system bus (5) and wherein each of the system processors may have access the local memory of another processor through its own local bus, its own interface unit, the system bus and the local bus of the other processor, deadlock is prevented by providing a bypass unit (40) of the interface unit (10) for enabling access from the system bus to the local bus through the bypass unit, a block (9) connected between the local bus and the interface unit (10) for latching system bus access requests received from an agent processor on the local bus, and a block (12) for isolation of the agent processor outputs from local bus, so that each agent processor may post read/write operations in the related latching block (9) for latching bus access requests and thereafter release its own local bus without awaiting completion of the operation, whereby the local bus is available to receive access requests received from the system bus through the bypass unit (40), the operation pending in the latching block (9) being completed, if a read operation, by reconnection of the agent processor (7) and the latching block (9) to the local bus. |
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DETAILED DESCRIPTION FIG.
1 shows in block diagram a multiprocessor system in accordance with the present invention.
The system comprises a plurality (for instance four) of central processing units or CPU 1, .
.
.
4.
The units are identical to each other in the architectural details which are shown with reference to CPU 1 only.
The several CPUs communicate with each other through a system bus (SB) 5.
In addition to the several CPUs, shared memories and input/output controllers, not shown, may be connected to the system bus 5.
A timing unit 6 provides timing signals required for operation of the system.
CPU1 comprises a processing unit 7 or microprocessor MP1, a local memory 8 (LM1) and an interface and arbitration unit 10 (INT & ARB) of the system bus.
Units 7,8,10 communicate with each other through a local bus 11.
More precisely, MP1 7 communicates with the local bus 11 through a control and isolation block 12 and the interface unit 10 communicates with the local bus 11 through a buffer output unit 9 or SBOUT and through an input block 40 or SBIN.
Access to local bus 11 from the several units is controlled by a control and arbitration block 13 or ARBT.
The interface unit 10 enables connecting system bus 5 to local bus 11, through block 40 when the request for access to local bus comes from the system bus, through block 9 when the requests for access to system bus comes from the local bus.
Interface unit 10 arbitrates control over the system bus together with the corresponding interface units of the other CPUs.
The units connected to the local bus are of two kinds: "masters", which can request and obtain access to the local bus, and "slaves" which are selected or referenced on master request.
Typically unit MP1 and the system bus as seen through unit 10 and block 40 are "master" units.
Local memory 8, and system bus, as seen through blocks 9 and 10 are "slave" units.
However, for the purpose of getting access to local bus, memory 8 and system bus may take the "master" role for performing the reply phase or reconnect operation required by read operations
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I/O Systems 
