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| It is accordingly an object of the present invention to provide a high-speed signal multiplexing ... |
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| In accordance with one embodiment of the invention a microcomputer device contains a CPU with an ... |
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| Partial scrolling video generator |
| OF SPECIFIC EMBODIMENTS The invention is described with reference to specific embodiments. Other ... |
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| Matrix display panel having alternating scan pulses generated within one frame scan period |
| It is an object of the present invention to provide a liquid crystal display panel having a high ... |
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| TDM system and method having time slot request signaling |
| Shown in FIG. 1 is an illustrative block diagram of a Time Division Multiplex (TDM) system 100 ... |
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| Vertical ramp automatic amplitude control |
| What is claimed is: 1. A method of producing a constant amplitude deflection ramp voltage over a ... |
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| Decision circuit operable at a wide range of voltages |
| What is claimed is: 1. A decision circuit, comprising: a first comparator which compares an input ... |
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| Communication path continuity verification arrangement |
| Time-slot Interchange Unit 11 Each of the line units transmits recurring frames each comprising 64 ... |
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Network monitoring system for cell delay variation
| Details |
Inventors: Cloutier, Leo; Curtis, David C.; Curtis, Kathleen P.; DeNunzio, David D.; Reed, William P.; Wolak, Robert A.;
Assignee: Bell Atlantic Network Services, Inc. (Arlington, VA)
Primary Examiner: Patel; Ajit
Assistant Examiner:
Attorney, Agent or Firm: McDermott, Will & Emery
An arrangement (apparatus and method) for monitoring jitter caused during transport of digitally-coded information in a packet switched network, and for managing network operations in accordance with the detected jitter. The detected jitter is used to determine whether corrective action is necessary, such as rerouting network traffic, or performing network maintenance. The disclosed arrangement detects program clock reference (PCR) values from an MPEG-encoded transport stream, whereby each pair of PCR values represents an expected arrival time of a corresponding stream segment. An actual arrival time for the corresponding stream segment is determined in response to detection of the corresponding PCR values and an independent clock signal. The expected arrival time of the stream segment and the actual arrival time are correlated with an accumulation of expected and actual arrivaimes of previously-received data packet stream segments in order to determine the jitter in the digital data stream. The jitter is corrected by a combination of adaptive buffering techniques and restamping the PCR value with corrected values coinciding with the actual arrival time of the stream segments. |
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DETAILED DESCRIPTION What is claimed is: 1.
An apparatus for minimizing jitter caused during transmission of a data packet stream, comprising: a time stamp detector detecting time stamp values within said data packet stream, each time stamp value representing an expected arrival time of a corresponding data packet stream segment; a timing circuit, responsive to a clock signal, for determining an actual arrival time for each said corresponding data packet stream segment; a detecting circuit detecting jitter in each data packet stream segment by executing a correlation of the corresponding expected arrival time and the corresponding actual arrival time with an accumulation of expected and actual arrival times of previously-received data packet stream segments; and a data packet stream correction circuit outputting said data packet stream as a corrected data packet stream having time stamp values adjusted in response to said correlation.
2.
An apparatus as in claim 1, wherein said data packet stream correction circuit comprises a timing restamp module replacing said time stamp values with corrected time stamp values in accordance with said correlation.
3.
An apparatus as in claim 2, wherein said data packet stream correction circuit further comprises a buffer circuit receiving said time stamp values.
4.
An apparatus as in claim 3, wherein said buffer circuit has an output data rate controlled in response to said correlation.
5.
An apparatus as in claim 3, wherein said buffer circuit selectively adjusts a spacing between packets in said data packet stream in accordance with said correlation.
6.
An apparatus as in claim 3, further comprising an independent clock source outputting said clock signal.
7.
An apparatus as in claim 1, wherein said data packet stream is received in MPEG format, said time stamp detector detecting said time stamp values as program clock reference (PCR) values from an MPEG stream having a selected program identifier (PID) value.
8.
An apparatus as in claim 7, wherein said data packet stream correction circuit comprises a buffer circuit receiving said MPEG stream for adjusting said time stamp values
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