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Home I/O Systems Non-hermetically-sealed-stackable-chip-carrier-package

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 Non-hermetically sealed stackable chip carrier package

Details
Inventors: Selinko, George J.;
Assignee: Motorola Inc. (Schaumburg, IL)
Primary Examiner: McQuade; John
Assistant Examiner: Paumen; Gary F.
Attorney, Agent or Firm: Motsinger; F. John, Gillman; James W.

An improved stackable integrated chip carrierassembly is disclosed which is especially suited for use in printed circuit board with dense configuration of components in limited areas of surface. The chip carrier assembly is mounted on an associated circuit board and allows the vertical stacking of active components in chip form, integral therein. The interconnections of the associated integrated circuit chips are accomplished without soldering which lends itself for easy disassembly when it becomes necessary to remove or replace an internal chip. The chip carrier assembly has an adaptable design allowing single or vertically stacked utilization of the module-like package. To achieve the necessary electrical isolation property, a ceramic cap is placed at the upper most position relative to the integrated module assembled package. This design has relatively few parts and allows smaller diameter wire to be used to achieve the required integrated circuit chip to package electrical bonding connections, when such is required.

DETAILED DESCRIPTION It is therefore an object of this invention to provide an improved stackable chip carrier package to be used with an associated integrated circuit or a plurality of integrated circuit devices, with or without electrical leads configuration, and which will overcome the foregoing deficiencies contained in the prior art.
Another object of this invention is to provide an improved vertically stackable integrated circuit module, consisting of a plurality of standard chip carrier packages utilizing an improved adaptable design, which will allow the single and/or the vertical stacking of the same integrated circuit component, yielding an improved volumetric efficiency of available design space parameters.
Still another object of the present invention is to provide an improved vertically stackable chip carrier package, wherein fewer parts are utilized, which will result in easier disassembly and removal of the housed integrated circuit chip will be facilitated Yet another object of the present invention is to provide an improved vertically stackable chip carrier package which will accomplish the necessary electrical interconnections of housed integrated circuits, without requiring solderability of such interconnections, to each vertically stacked package, comprising the overall integrated circuit module thereof, and which will result in greater reliability of the associated integrated circuit chip interconnections therein.
In practicing the invention, an improved stackable chip carrier assembly is provided for use in electronic apparatus which will accommodate a plurality of vertically stacked integrated circuit devices and provide for a solderless electrical connection to a printed circuit board.
The assembly includes a stacked array of interfitting spacer members of substantially equal size and dimension having a central cavity for accommodating a respective associated integrated circuit device therein and a plurality of elongated slots positioned around the periphery of said spacer member and extending therethrough



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