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Optically triggered lateral thyristor with auxiliary region
| Details |
Inventors: Herman, Thomas;
Assignee: International Rectifier Corporation (Los Angeles, CA)
Primary Examiner: James; Andrew J.
Assistant Examiner: Mintel; William A.
Attorney, Agent or Firm: Ostrolenk, Faber, Gerb & Soffen
An optically triggered lateral thyristor consists of a plurality of individual lateral thyristor elements connected in parallel. Each element has an active base region which contains a respective cathode region. Each of the base regions is carried in a common conductivity type body. Extending fingers of a continuous anode electrode partly enclose each individual base region to enable the parallel connection of the individual devices. The thyristor base and emitter zones are surrounded by an auxiliary P region which is resistively connected to a field plate and the cathode electrode to improve emitter collection efficiency. The cathode electrode and anode electrode are interdigitated. The cathode electrode is connected to spaced, parallel, generally rectangular emitter regions which are disposed in respective bases between loops of the cathode electrode. Radiation applied to the surface of the device by a noncritical photo source produces the effect of a gate current in order to turn on the device. A resistor, zener diode, capacitor and a plurality of parallel connected MOSFETs are integrated into the chip to define a control circuit for controlling the turn-on of the main lateral thyristor. The anode region may be relatively heavily doped to reduce forward drop. The emitter region surface may be relatively lightly doped to improve injection efficiency of the emitter. |
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DETAILED DESCRIPTION OF THE DRAWINGS Referring first to FIG.
1, there is shown therein in cross-section the junction pattern and metallizing of a lateral thyristor chip which is manufactured in accordance with some of the principles of the present invention.
The chip containing the lateral thyristor of FIG.
1 can have any desired size and configuration, and is a chip of monocrystalline silicon.
The various junctions shown in FIG.
1 are formed in N(--) layer 20.
Layer 20 may have a resistivity of about 20 ohm-centimeters.
Spaced P type regions 21, 22 and 23 are formed in the upper surface of chip 20 by any desired process.
A further P type region 23a, which is inactive, may enclose the periphery of region 23.
Regions 21, 22, 23 and 23a can be boron-diffused regions of sufficient concentration so that the sheet resistance of the P regions will be about 1,600 ohms per square at the chip surface.
They may also be formed, for example, by an ion implantation and drive-diffusion process employing 5.
times.
10.
sup.
+13 boron atoms per square centimeter dose so that it is relatively lightly doped.
Region 21 is preferably more heavily doped than the other P regions.
Regions 21, 22, 23 and 23a may have the same depth of approximately 4 microns.
P type region 23 contains an N(+) region 24 to complete the laterally spaced junctions of the lateral thyristor.
The facing edges of regions 21 and 23 should be as close together as possible while still being able to block a selected voltage.
In the present application, the device preferably blocks about 400 to 500 volts and a spacing of 105 microns is used.
Region 21 is the anode region, region 23 is the gate or base region, region 24 is the emitter or cathode region while the N(--) body 20 is the main blocking region of the thyristor shown in FIG.
1.
Region 22 is a known type of floating guard region which permits an increase in the blocking voltage between junctions 21 and 23 to as high as 400 to 500 volts without danger of breakdown at the surface of the chip
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I/O Systems 
