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Paged memory management unit which locks translators in translation cache if lock specified in translation table
| Details |
Inventors: Keshlear, William M.; Cohen, Robert B.;
Assignee: Motorola, Inc. (Schaumburg, IL)
Primary Examiner: Heckler; Thomas M.
Assistant Examiner:
Attorney, Agent or Firm: Fisher; John A., Van Myers; Jeffrey
In a data processing system, a paged memory management unit (PMMU) translates logical addresses provided by a processor to physical addresses in a memory using translators constructed from page descriptors comprising, in part, translation tables stored in the memory. The PMMU maintains a set of recently used translators in a translator cache. In response to a particular lock value contained in a lock field of the page descriptor for a particular page, the PMMU sets a lock indicator in the translator cache associated with the corresponding translator, to preclude replacement of this translator in the translator cache. A lock warning mechanism provides a lock warning signal whenever all but a predetermined number of the translators in the cache are locked. In response, the PMMU can warn the processor that the translator cache is in danger of becoming full of locked translators. Preferably, the PMMU is also inhibited from locking the last translator in the cache. |
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DETAILED DESCRIPTION Accordingly, it is an object of the present invention to provide a mechanism which allows a paged memory management unit to determine automatically from a field in each page descriptor in the translation tables whether the corresponding translator should be locked in the translation cache. Another object of the present invention is to provide an efficient way to indicate, in a field in each page descriptor in the translation tables, that certain translators are to be locked in the translation cache. In carrying out these and other objects of the present invention, there is provided, in one form, a paged memory management unit (PMMU) adapted to translate each of a plurality of logical addresses into a corresponding physical address using a selected one of a plurality of page descriptors comprising one or more translation tables stored in a memory, the PMMU assembling each of said logical addresses and the corresponding physical address into a respective translator. In the preferred form, the PMMU includes: a cache having a plurality of storage locations for storing the translators, each storage location having an associated lock indicator adapted to be selectively set; and control logic for storing a translator in a selected one of the storage locations only if the associated lock indicator is reset, the control logic setting the lock indicator of that storage location only in response to a lock signal associated with the translator. According to the present invention, the lock signal comprises a lock bit stored in the memory as a portion of the page descriptor used by the PMMU to assemble each translator, the control logic being responsive to the state of this lock bit to selectively set the lock indicator associated with the storage location selected to store the respective translator.
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