Parallel test circuit for semiconductor memory device

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Reference will now be made in detail to the preferred embodiment of the present invention, examples of which are illustrated in FIGS.
8-15 of the accompanying drawings.
FIG.
8 depicts a data path of a parallel test circuit in accordance with a first preferred embodiment of the present invention.
A memory array of FIG.
8 includes multiple memory banks, and each memory bank is divided into a predetermined number of memory blocks.
A 4- or 16-Mega byte memory device could be divided into 4 memory banks and 16 memory blocks.
A memory array of two memory banks and four memory blocks is shown in FIG.
8.
In each memory block there are a predetermined number of data output (DO) lines, a DO line multiplexer S7 (DO MUX) is electrically connected to the DO lines, and a one/zero/hi-Z comparator S8 also connected to the DO lines.
Each output terminal of the DO MUX S7 and the one/zero/Hi-Z comparator S8 is connected in common with a predetermined number of first data buses (FDB).
In the circuitry of FIG.
1, since there are four memory blocks, the number of the FDBs is four.
The FDBs are electrically connected to an input terminal of the first data bus comparator S9 (FDB comparator).
The FDB comparator S9 has an output terminal connected to second data buses SDBs.
The SDBs are connected to a merged data bus (MDB) via NAND gate 10.
The MDB is connected by DB MUX S10 to the data bus (DB) switch (0/1) and the DB switch (0/1/Hi-Z) S11.
The DB switch (0/1) and the DB switch (0/1/Hi-Z) have each output end connected to the input terminal of data output buffer DOUT S12.
The lower part of FIG.
8's circuit is of construction similar to the above-described upper part.
Description of the specific structure of the DB switch S11 is unnecessary because the operation and function are analogous to those of circuit S1 and S2 as shown in FIG.
1 and known in the art.
Differences between the circuits of FIGS.
1 and 8 are described as follows.
As shown in FIG.
8, two switches are alternatively connected between the DB MUX S10 and DOUT S12, instead of the one/zero comparator incorporated in the circuitry of FIG