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Home I/O Systems Pipeline-data-processor-with-arithmetic-logic-unit-capable-of-performing-different-kinds-of-calculations-in-a-pipeline-stage

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Details
Inventors: Matsuzaki, Toshimichi; Higaki, Nobuo; Deguchi, Masashi;
Assignee: Matsushita Electric Industrial Co., Ltd. (Osaka, JP)
Primary Examiner: Donaghue; Larry D.
Assistant Examiner: Harrity; John
Attorney, Agent or Firm: McDermott, Will & Emery

The data processors of the present invention transfer the contents of address registers and program registers through an unused bus during the cycle of writing into registers and execute, in one cycle, a load instruction or a store instruction that requires address calculation, although the processors have two buses and one arithmetic/logic unit. Also, the data processors assign basic arithmetic instructions between registers and load/store instructions instruction codes having a basic instruction word length of one byte by functionally dividing general purpose-registers into four address registers and four data registers.

DETAILED DESCRIPTION The object of the present invention is therefore to provide a data processor that calculates addresses at high speed by means of low cost hardware having two internal buses and one arithmetic/logic unit and improves performance in executing memory access instructions and jump instructions and the like.
The present invention is also aimed at providing a data processor that has 8 registers and still realizes basic arithmetic/logic instructions between registers and load/store instructions by 8-bit instruction codes.


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