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 Programmable logic module and architecture for field programmable gate array device

Details
Inventors: El-Avat, Khaled A.; Kaptanoglu, Sinan; Chan, King W.; Plants, William C.; Lien, Jung-Cheun;
Assignee: Actel Corporation (Sunnyvale, CA)
Primary Examiner: Hudspeth; David R.
Assistant Examiner:
Attorney, Agent or Firm: D'Alessandro & Ritchie

A user-programmable gate array architecture includes an array of logic function modules which may comprise one or more combinatorial and/or sequential logic circuits. An interconnect architecture comprising a plurality of horizontal and vertical general interconnect channels, each including a plurality of interconnect conductors some of which may be segmented, is imposed on the array. Individual ones of the interconnect conductors are connectable to each other and to the inputs and outputs of the logic function modules by user-programmable interconnect elements. A local interconnect architecture comprising local interconnect channels is also imposed on the array. Each local interconnect channel includes a plurality of local interconnect conductors and runs between pairs of adjacent ones of the logic function modules.

DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT Those of ordinary skill in the art will realize that the following description of the present invention is illustrative only and not in any way limiting.
Other embodiments of the invention will readily suggest themselves to such skilled persons.
Referring first to FIG.
1, a simplified block diagram of an FPGA core architecture 10 according to the present invention is shown.
As used herein the term "core architecture" refers to the architecture of the core of an FPGA array which comprises a plurality of logic function circuits or modules (reference numerals 12-1 to 12-12) arranged in a matrix with an overlay of interconnect architecture including interconnect conductors and user-programmable interconnect elements.
The logic function modules 12-1 through 12-12 may comprise any of a variety of circuits, either combinational logic, sequential logic, or combinations thereof, and need not be identical, as will be disclosed in more detail herein with respect to a presently preferred embodiment of the invention.
As shown in FIG.
1, logic function modules 12-1 through 12-12 are disposed in a network of interconnect conductors.
In order to avoid overcomplicating the figure and rendering it more difficult to comprehend, those of ordinary skill in the art will recognize that the network of interconnect conductors is shown in simplified schematic form.
In addition, while the drawing shows the interconnect conductors running between the logic function circuits, those of ordinary skill in the art will readily recognize that the architecture may be a "sea of gates" type architecture where the interconnect conductors actually run directly over, rather than between, the logic function circuits.
In virtually all cases, the interconnect conductors will comprise metal lines in layers disposed over the layers which constitute the logic function circuits.
Such a "sea of gates" architecture is known in the art and is exemplified by U.
S.
Pat.
No.
5,132,571 to McCollum et al



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