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Data processing system having interlinked slow and fast memory means
In accordance with the present invention, there is provided a data processing system having a large capacity first read only memory having a first access time, and a ...
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Semiconductor memory having subarrays and partial word lines
I claim: 1. A semiconductor array memory comprising a plurality of selectable subarrays arranged on a chip having a common decoder, common read lines and common write ...
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Flat-cell read-only-memory integrated circuit
OF THE PREFERRED EMBODIMENT A detailed description of the preferred embodiments of the present invention is described with reference to FIGS. 1-8. FIGS. 1-3 illustrate ...
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Variable sized FIFO memory and programmable trigger level therefor for use in a UART or the like
In accordance with the illustrated embodiments, the present invention provides a data available interrupt circuit with a variable threshold for reading data from a ...
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Apparatus for programmable circuit and signal switching
We claim: 1. A programmable interconnect device for routing signals between signal ports in response to data from an external controller, the device comprising: switch ...
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Semiconductor memory device having hierarchical bit line structure employing improved bit line precharging system
Accordingly, a first object of the present invention is to provide a semiconductor memory device of a hierarchical bit line structure having a high read rate. Another ...
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Dram core refresh with reduced spike current
The present invention makes multibank refresh more practical by varying the current profile for the row sense and/or row precharge currents during a refresh operation, ...
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Shape memory alloy optical fiber switch
In FIG. 1, a switch is shown as a double pole switch. That is, two sets of fibers are switched and released at the same time. However, this is not a limitation of the ...
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Semiconductor memory device with reduced inter-band tunnel current
Accordingly, it is a general object of the present invention to provide a semiconductor memory device which can satisfy the need described above. It is another and more ...
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Circuitry and method for addressing global array elements in a distributed memory, multiple processor computer
OF INVENTION FIG. 2 illustrates in block diagram form a distributed memory computer 20, which implements the global addressing scheme of the present invention. As will ...
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