Pseudo-concurrent access to a cached shared resource

DETAILED DESCRIPTION A method and apparatus is disclosed for efficiently controlling the access to a cached shared resource such as dynamic random access memory (DRAM).
The access is effected in a pseudo-concurrent manner by two devices such as a central processing unit (CPU) and a bus master agent.
While one device accesses data stored in the DRAM, the other device accesses a copy of the DRAM data which is stored in the cache of the shared resource.
One embodiment of the present invention is a computer system which includes: a CPU, a bus master agent, a host bus, a peripheral component interconnect (PCI) bus, a DRAM shared memory resource which stores addressed data, a memory cache for the DRAM, and a controller for controlling access by the CPU and bus master devices to the addressed data.
The addressed data stored in the DRAM has first and second data portions.
A copy of the first data portion is stored in the cache.
The control apparatus is coupled to the DRAM and the cache.
The host bus, which includes an address bus, is coupled between the controller and the CPU.
The peripheral component bus is coupled between the controller and the bus master.
The controller has an arbitrator which senses when the CPU is to access the first data portion and then grants the CPU access to the first data portion When the CPU has been granted access to the first data portion, an address latch stores the starting address of the first data portion.
The control apparatus also has address bus suspension circuitry.
If, while the CPU is accessing the first data portion, the arbitrator senses that the bus master is to access the second data portion, the arbitrator signals the suspension circuitry.
When the suspension circuitry senses that the latch has stored the starting address, the suspension circuitry causes the CPU to tri-state the address bus.
Once the arbitrator senses that the address bus is tri-stated, the arbitrator grants the bus master access to the second data portion.
In this way, the bus master accesses the second data portion of the DRAM concurrently with access by the CPU to the cached first data portion