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RC netlist reduction for timing and noise analysis
| Details |
Inventors: Yang, Xiao-Dong;
Assignee: Sun Microsystems, Inc. (Santa Clara, CA)
Primary Examiner: Whitmore; Stacy A.
Assistant Examiner:
Attorney, Agent or Firm: Rosenthal & Osha L.L.P.
A circuit reduction method that generates a netlist that maintains a topology of an original circuit while preserving an original circuit's functions and characteristics is provided. Further, a circuit reduction method that allows a user to selectively determine which nodes of an original circuit to reduce is provided. Further, a circuit reduction tool that is capable of removing loops that are not present in an original circuit but are present in an extraction of the original circuit is provided. |
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DETAILED DESCRIPTION Embodiments of the present invention relate to a method and apparatus for generating a netlist that maintains a topology of an original circuit while preserving an original circuit's functions and characteristics.
Embodiments of the present invention further relate to a method and apparatus for reducing a circuit using a process that maintains both (1) an original circuit topology and (2) functional characteristics of the original circuit.
FIG.
3 shows an exemplary flow process in accordance with an embodiment of the present invention.
Initially, a detailed standard parasitic format ("DSPF) is read (step 40).
The DSPF has information regarding a structure of an original circuit.
Once the DSPF has been read (step 40), a preprocessing phase occurs (step 42).
The preprocessing phase involves preparing the original circuit such that it can be reduced.
Thereafter, one or more nodes of the original circuit are sorted based on resistive degrees of the one or more modes (step 44).
Then, a timer is used to measure one or more time constants of the original circuit (step 46).
Once the time constants have been determined (step 46), the time constants are evaluated and sorted (step 48).
Using the evaluated and sorted time constant information, one or nodes in the original circuit are analyzed (step 50) in order to determine which loops of the original circuit to eliminate (step 52).
Once one or more loops are eliminated from the original circuit, a time measurement may again be made (step 46) to determine one or more time constants of the modified circuit.
After the loops are removed (step 54), a reduced circuit results, where after, the reduced circuit is post-processed and stored in a new DSPF file (step 56).
FIG.
4a shows a circuit for a reduction process in accordance with an embodiment of the present invention.
Particularly, FIG.
4a shows a model of a node.
In the reduction process, resistances and ground capacitances are redistributed by eliminating nodes with insignificant characteristic time constants based on local circuit transformation in order to keep an Elmore time constant from all directions
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I/O Systems 
