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Re-configurable-block-length-cache

Devices, systems and methods for accessing data using a pixel preferred data organization

According to the invention, a processing system is provided operating on data words each having at ...

Technique for accessing and refreshing memory locations within electronic storage devices which need to be refreshed with minimum power consumption

This and additional objectives are accomplished by the various aspects of the present invention, ...

Display apparatus

The present invention has been attempted to solve the above-described problems, and therefore, has ...

Video timing and display ID generator

The invention provides an improved video timing generator and display ID generator that function at ...

Digital recorder for processing in parallel data stored in multiple tracks

It is therefore an object of the present invention to provide a digital recorder which is designed ...

System for executing, canceling, or suspending a DMA transfer based upon internal priority comparison between a DMA transfer and an interrupt request

An object of the present invention is to provide a data processing device capable of shortening the ...

Photographic order matching method and apparatus

In accordance with the foregoing objects the invention contemplates an apparatus in which ...

Circuitry for transferring data from a data bus and temporary register into a plurality of input registers on clock edges

In accordance with the present invention, a floating point processor is provided which ...

Branch prediction and resolution apparatus for a superscalar computer processor

The present invention provides an apparatus and method for improving the performance of superscalar ...

Compressed Instruction format for use in a VLIW processor

OF THE PREFERRED EMBODIMENT FIG. 1a shows the general structure of a processor according to the ...

Re-configurable block length cache

Details

Inventors: Schnizlein, Paul G.; Walters, Jr., Donald M.;
Assignee: Advanced Micro Devices,Inc. (Austin, TX)
Primary Examiner: Bowler; Alyssa H.
Assistant Examiner:
Attorney, Agent or Firm: Foley & Lardner

A cache organizational signal ("CORG signal") selects between cache organizations. A cache organization is chosen according to the speed of the main memory that is paired with the cache to handle different size blocks of instructions. When the CORG signal organizes the cache to handle blocks having few instructions per block, many blocks are present and a higher hit rate occurs, which works well with a fast main memory. When the CORG signal organizes the cache to handle blocks having more instructions per block, fewer blocks are present, a lower hit rate occurs, and processor idle cycles decrease, which works well with a slower main memory.

DETAILED DESCRIPTION The invention concerns a cache having a cache memory for storing a plurality of data words, such as, instruction words in blocks of memory.
The cache has a mechanism for selecting between a first cache organization defining a first block having a first number of instructions and a second cache organization defining a second block having a second number of instructions different than the first number of instructions.
The cache utilizes a cache organization signal that indicates cache selection.
The number of instructions in the block depends upon the selected cache organization.
The specification describes an embodiment of the invention in which a cache has selectable organization.
The cache is organized so that the number of instructions in a block is selected to match the speed of the main memory that is paired with the cache.

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