Read only memory and decode circuit

DETAILED DESCRIPTION Accordingly, it is an object of this invention to provide an improved form of data path multiplexing and busing structure.
It is a further object of the invention to provide an I.
sup.
2 L integrated circuit having proper biasing conditions across the whole circuit with an injection bus of reduced width.
It is still another object of the invention to provide an improved register file cell design for a microprocessor integrated circuit It is still another object of the invention to provide an improved timing circuit for a register file cell in acordance with the invention.
It is yet another object of this invention to provide an organization for a ROM which allows efficient layout of the ROM in a microprocessor integrated circuit.
It is another object of the invention to provide such a ROM organization which allows rapid accessing of microcode stored in the ROM.
A microprocessor integrated circuit in accordance with this invention has a register file with a first plurality of registers.
Each of the first plurality of registers is connected to one of a second plurality of local busses.
The local busses are connected to a main bus by a multiplexing means.
In accordance with a further aspect of the invention, the microprocessor integrated circuit has a main injector bus and a ground return bus in a data path.
There is at least one branch ground bus.
A ground balancing resistor connects the ground return bus and the branch ground bus.
In yet another aspect of the invention, a memory storage circuit has a latch with a pair of outputs.
There is a data input to the latch and an enable signal input to control the data input to the latch.
The storage circuit includes a pair of output enable signal inputs, each of which is connected to control one of the pair of outputs.
In still another aspect of the invention, a timing circuit has a delay means connected to receive input timing pulses generated in response to a plurality of inputs.
An output of the delay means is connected to supply delayed timing pulses to an output gate