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Readout-circuit-and-method-for-multiphase-memory-array

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Details

Inventors: Von Flue, Timothy A.;
Assignee: Tektronix, Inc. (Beaverton, OR)
Primary Examiner: Shaw; Gareth D.
Assistant Examiner: Ray; Gopal C.
Attorney, Agent or Firm: Griffith; Boulden G.

A multiphase memory array is read out using two multiplexers and a demultiplexer under the control of a state machine. The state machine enables one portion of the memory array at a time using a gate to multiplex the memory portion outputs. While a particular portion is enabled, a bit multiplexer associated with that portion is directed by the controlling state machine to sequentially select each bit at the current address in that memory portion for output. A shift register demultiplexer performs serial to parallel conversion on the sequential bits from each memory portion to convert them to a readback byte or word for output. After the byte or word has been read out, the state machine enables the next portion of the memory array and repeats the multiplexing and demultiplexing process for the data at the same address in that memory portion. When all of the memory portions have read out, the address to the memory array is changed and the whole process is repeated for the data at the new address.

DETAILED DESCRIPTION Two multiplexers, one demultiplexer, and a state machine that controls the operation of the multiplexers and the demultiplexer are used to read data out of a multiphase memory array having a number of memory portions.
For a given address in the multiphase memory array, the controlling state machine directs a first multiplexer to enable input from the first of the memory portions in the array.
A second multiplexer, associated with that memory portion, sequentially selects for readback one bit at a time from the data byte or word stored at that particular address in the enabled memory portion.
The serial stream of data bits from the second multiplexer passes through the first multiplexer to the demultiplexer which reconstructs by serial to parallel conversion the data byte or word that was stored at that address in the first memory portion.
That byte or word is then read out of the memory array by an external device.
Next, the first multiplexer is directed to enable input from the next memory portion, where the next byte or word of data is stored at the same address.
The second multiplexer which is associated with the next memory portion then selects in sequence each bit in the byte or word at this location in this memory portion.
The resulting stream of data bits passes through the first multiplexer to the demultiplexer, where it is converted by serial to parallel conversion into the next byte or word of data for readout by the external device.
This process continues for each memory portion in the multiphase array, each time reading from the location addressed by the same address.
When all of the data has been sequentially read from that address in every portion of the memory array, the address being applied to the whole memory array is advanced and the controlling state machine is reset to its initial condition, causing the first memory portion to be enabled again so that the whole process may be repeated for the plurality of data bytes or words stored at the next address in the array

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