Real time digital signal processor idle indicator

DETAILED DESCRIPTION OF THE DRAWINGS FIG.
1 is a schematic block diagram of the presently preferred exemplary embodiment of a digital signal processing system 10 in accordance with the present invention.
System 10 includes a central processing unit ("CPU") or processor 12.
Processor 12 may, for example, be a conventional microprocessor including a read only memory program store 12a, internal registers and an arithmetic logic unit, etc.
--or virtually any other type of device which processes digital signals.
A conventional clock signal generator 13 produces a periodically-alternating digital clock synchronization signal which drives processor 12.
The frequency (that is--the period) of this clock signal determines the time it takes for the processor 12 to execute each of its program control instructions.
In the preferred embodiment, processor 12 may be connected to a variety of associated conventional external circuits which perform various desired functions.
For example, if processor 12 is to be used to provide digital filtering, it may be connected to the output of an analog-to-digital converter or other source of digitized signals (not shown).
Processor 12 may also be connected to display devices, input/output peripheral devices, or virtually any of the thousands of different devices designed to be interfaced with a processor (all as is well known to those skilled in this art).
In the preferred embodiment, processor 12 includes at least one unused data output connection P1 which is connected to the input of a conventional input/output (I/O) register 14.
I/O register 14 is sensitive to the "edges" (transitions) of the P1 output of processor 12 and produces an output signal "BIT" which changes state in response to those edges.
In the preferred embodiment, register 14 buffers the signal outputted at the processor P1 data output, but does not alter the frequency of that signal (and may but need not necessarily synchronize the signal to the processor clock).
The register 14 "BIT" output is connected to the input of a frequency counter 16 operating as an event counter with a fixed gate time (of, e