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SCSI host adapter integrated circuit utilizing a sequencer circuit to control at least one non-data SCSI phase without use of any processor
| Details |
Inventors: Stuber, Craig A.; Young, Byron Arlen;
Assignee: Adaptec, Inc. (Milpitas, CA)
Primary Examiner: Ellis; Richard L.
Assistant Examiner:
Attorney, Agent or Firm: Skjerven, Morrill, MacPherson, Franklin & Friel, Gunnison; Forrest E.
A single chip circuit is used in combination with a host system microprocessor to provide host-adapter functions for a SCSI interface. The host adapter integrated circuit includes a 128 byte DMA FIFO, a 8 byte SCSI FIFO, hardwired automatic sequencers for the SCSI ARBITRATION and SELECTION phases, hardware interrupt generating circuitry, two clock sources, a register set and a powerdown capability. The host computer system microprocessor is used to perform selected SCSI phases. Other SCSI phases are performed automatically by the integrated circuit of this invention. When a delay in a SCSI phase is anticipated, according to the principles of this invention control of the microprocessor is returned to the host computer system. Hence, the microprocessor may execute a user application while the integrated circuit simultaneously performs one or more SCSI phases. When the SCSI phase is complete or other predetermined conditions occur on the SCSI bus, a hardware interrupt is sent to the microprocessor. In response to the interrupt, the microprocessor is available to support further SCSI operations by the integrated circuit of this invention. |
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DETAILED DESCRIPTION According to the principles of this invention, a host/adaptor (H/A) integrated circuit is a computer bus to SCSI bus controller.
The host/adaptor (H/A) integrated circuit of this invention allows the host computer to access a SCSI bus with flexibility while at the same time automating the more time consuming SCSI functions such as target selection and reselection.
Data transfer between the SCSI bus and the computer data bus is accomplished with either DMA (Direct Memory Access) or PIO (Programmed Input Output) using a data path which preferably has the same width in bits as the computer data bus.
Unlike the prior art host/adapter systems, the H/A integrated circuit of this invention is preferably mounted on the computer system motherboard so that a separate host/adapter board is unneeded.
Moreover, a processor dedicated solely to SCSI operations has been eliminated.
The H/A integrated circuit of this invention uses the processor of the host computer system, sometimes called a central processing unit(CPU) or a microprocessor, to perform selected operations so that the H/A integrated circuit does not include a processor.
The host computer system processor is interrupted by a signal, a system hardware interrupt, from H/A integrated circuit when the processor is needed to support SCSI operations.
Unlike the prior art systems that placed the processor in a wait state, the processor stops processing the user application and turns control of the processor over to a driver for the H/A integrated circuit.
The driver uses the processor to perform required SCSI operations.
If the driver determines that the SCSI operations performed by the H/A integrated circuit will take some time, the necessary instructions for continued SCSI operations are provided to the H/A integrated circuit and control of the processor is returned to the host computer system.
Thus, the processor is available for execution of user applications while the H/A integrated circuit of this invention simultaneously performs a predetermined SCSI phase or phases
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I/O Systems 
