Self-regulating clock generator

DETAILED DESCRIPTION The invention therefore provides a clock generator for providing an output clock signal for clocking a microprocessor having first and second speed paths requiring first and second minimum execution time periods wherein the output clock signal has, during each period, a first phase to establish a first execution time period for the processor sufficient to accommodate a first speed path during the first phase and a second phase to establish a second execution time period for the processor sufficient to accommodate the second speed path during the second phase.
The output clock signal is provided responsive to an externally applied input clock signal having a frequency and a duty cycle within a wide range of frequencies and duty cycles.
The clock generator includes latch means having an input arranged to receive the input clock signal and an output, and is also arranged to be set and reset by the input clock signal, when enabled, for providing the output clock signal at the output and enable means coupled to the latch means to enable the setting and resetting of the latch means by the input clock signal after the first and second execution time periods have elapsed.
The present invention further provides a self-regulating clock generator for generating an output clock signal for clocking a microprocessor having speed paths requiring minimum execution times wherein the output clock signal has a duty cycle and a frequency to provide execution times sufficient to accommodate the speed paths and is generated in response to an applied input clock signal having a frequency and duty cycle within a wide range of frequencies and duty cycles.
The clock generator includes latch means having an output for providing the output clock signal and input conditioning means having a first input coupled to the input clock signal, a second input, and an output coupled to the latch means for setting and resetting the latch means to cause the latch means to provide the output clock signal.
The clock generator further includes delay means coupled between the latch means output and the input conditioning means second input for delaying the application of the output clock signal to the input conditioning means second input by a time sufficient to accommodate the speed paths of the microprocessor