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Semiconductor integrated circuit device
| Details |
Inventors: Miyaoka, Shuuichi; Miyamoto, Kazuhisa; Odaka, Masanori; Sawamoto, Hideo; Nakayama, Michiaki; Kusunoki, Mitsugu; Ikeda, Masato; Ogata, Takashi; Kobayashi, Kouji; Kato, Masao; Sumimoto, Tsutomu;
Assignee: Hitachi, Ltd. (Tokyo, JP); Hitachi Microcomputer System, Ltd. (Tokyo, JP)
Primary Examiner: Popek; Joseph A.
Assistant Examiner:
Attorney, Agent or Firm: Antonelli, Terry, Stout & Kraus
A semiconductor integrated circuit device such as a memory device with logic function comprises a plurality of RAM macrocells and gate arrays. The RAM macrocells are constituted by bipolar CMOS RAMs having a total memory capacity of at least 100 kilobits, and the gate arrays contain at least 4000 gates. The logic circuits in the memory device with logic function or the like are constructed by selectively combining CMOS, bipolar CMOS or ECL gate circuits depending on the output load capacity, transmission characteristic requirement, power dissipation and required layout area. The level of signals at various circuits is set to the ECL level or MOS level depending on the local circuit configuration and other factors. The memory device further incorporates sequence control circuits required to be installed downstream of buffer storages of computers. |
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DETAILED DESCRIPTION It is therefore an object of the present invention to provide a semiconductor integrated circuit device which optimizes the circuit and signal configuration of a memory device with logic function or the like in order to enlarge the circuit integration thereof and to reduce the power dissipation thereby.
It is another object of the present invention to provide a semiconductor integrated circuit device which optimizes the sharing of functions between the buffer storage comprising a memory device with logic function for a computer or the like on the one hand, and other devices on the other, so as to obtain a high-speed system.
It is a further object of the present invention to provide a semiconductor integrated circuit device comprising a plurality of means for enlarging the circuit integration of a memory device with logic function and of computers or the like containing the memory device, for stabilizing the performance of the memory device and computers, and for boosting the operation speed thereof, whereby-enhancing the ability thereof to be diagnosed.
The above and other related objects and features of the invention, as well as the novelty thereof, will clearly appear from the following description and from the accompanying drawings.
According to one aspect of the invention, there is provided a semiconductor integrated circuit device such as a memory device with logic function, the device comprising a plurality of RAM macrocells and gate arrays, the RAM macrocells being constituted by bipolar CMOS RAMs with a total memory size of at least 100 kilobits, the gate arrays containing at least 4K bipolar CMOS gates.
The logic circuits for the memory device with logic function or the like are constituted by selectively combining CMOS, bipolar CMOS or ECL gate circuits in accordance with such parameters as output load capacity, required transmission characteristic, power dissipation and required layout area.
The signal level at various parts is either the ECL level or the MOS level depending on the circuit configuration
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I/O Systems 
