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Details
Inventors: Iwata, Yoshihisa;
Assignee: Kabushiki Kaisha Toshiba (Kawasaki, JP)
Primary Examiner: Wamsley; Patrick
Assistant Examiner:
Attorney, Agent or Firm: Banner & Witcoff, Ltd.

A data transmission system is provided including a clock source, semiconductor integrated circuit devices, a controller configured to control the semiconductor integrated circuit devices, and a clock signal pass connected to the clock source, the controller and the semiconductor integrated circuit devices. The data transmission system may include a daisy chain data pass connected to the controller and the semiconductor integrated circuit devices, and a two-way data strobe signal pass connected to the controller and the semiconductor integrated circuit devices. The clock source, the semiconductor integrated circuit devices and the controller transmit and receive therebetween a clock signal via the clock signal pass. The semiconductor integrated circuit devices and the controller transmit and receive therebetween multi-valued current data via the daisy chain data pass, and a data strobe signal in the form of a binary voltage signal via the two-way data strobe signal pass.

DETAILED DESCRIPTION OF THE INVENTION To begin with, the present invention will be outlined.
A data transmission system according to the present invention and a LSI suitable therefor are characterized in that transmission of data or signals is performed between semiconductor integrated circuit devices by current data or signals which are represented in multiple-value form.
In a case that current transmission of data is performed, it is desired that one-to-one correspondence is formed between the transmission side and the reception side.
Accordingly, when a large amount of data/signals is transmitted/received in a simple manner, the number of data lines/signal lines must be increased.
To avoid the increased bus width, data (current) is represented in multiple-value form, taking advantage of the fact that the current has an additive nature.
The multi-value representation of current provides a wider noise margin as compared with a multi-value representation of voltage.
Also, the multi-value representation of data (current) enables transmission/reception of a large amount of data even with a transmission means driven by a low speed synchronization clock.
In the following, various embodiments of the present invention will be described with reference to the accompanying drawings.
<First Embodiment> FIG.
1 is a block diagram illustrating a portion of LSIs according to a first embodiment.
Specifically, FIG.
1 schematically illustrates the configuration of system in which a data output circuit portion of a first LSI (CHIP-A) 11 outputs a current, and a data input circuit portion of a second LSI (CHIP-B) 12 receives the current.
That is, the data output circuit portion of the first LSI 11 comprises a digital-to-analog converter (DAC) 14 for converting binary voltage data output from an internal circuit 13 to multi-value data; and an output buffer PMOS transistor 15 for outputting an output DACout of the DAC 14 to an external data line 1 as a multi-value current.
The data input circuit portion of the second LSI 12 which receives the multi-value current from the external data line 1 comprises an input buffer NMOS transistor 16 for receiving the incoming current from the external data line 1; an NMOS transistor 17 connected to the transistor 16 in current mirror configuration; and an analog-to-digital converter (ADC) 19 for converting a current ADCin flowing into the transistor 17 to binary voltage data and supplying the converted binary voltage data to an internal circuit 18



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