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Semiconductor memory device and method thereof
| Details |
Inventors: Gil, Gyoung-Seon;
Assignee: LG Semicon Co., Ltd. (Cheongju, KR)
Primary Examiner: Nguyen; Tan T.
Assistant Examiner:
Attorney, Agent or Firm: Fleshner & Kim
A semiconductor memory device and a fabrication method thereof include formation of surplus gates connected to a cell node of a gate edge region, located at a cell node side of a SRAM access transistor, and to the gate of a driving transistor located at the opposite side thereof. The present invention prevents silicon loss of the substrate caused by the formation of a buried contact in the conventional device, secures an operational stability of the memory cell by controlling differently the current flow of an access transistor in accordance with the condition of the cell node (for example, low level or high level), and facilitates an interconnection in the cell since the gate of a side transistor is used as a substitute for another interconnection (for example, a wiring) when realizing a SRAM. Further, during a reading operation, since the resistance of the n+ source region of the cell node of the access transistor is larger than that of the drain region connected to the bit line, the current driving ability is made lower, and the operational stability is enhanced. |
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DETAILED DESCRIPTION I claim: 1.
A memory device, comprising: a) a plurality of wordlines and bitlines; b) a plurality of memory cells, each memory cell being responsive to corresponding wordline and bitline and each cell having i) a latch coupled between a first node for receiving a first predetermined potential and a second node for receiving a second predetermined potential; ii) a first transistor coupled to said latch at a third node, and said corresponding wordline and bitline; iii) a second transistor coupled to said latch at a fourth node, and said corresponding wordline and bitline; and iv) means for controlling a current flow in at least one of said first and second transistors.
2.
The memory device of claim 1, wherein said controlling means comprises: a third transistor coupled to said third node; and a fourth transistor coupled to said fourth node.
3.
The memory device of claim 1, wherein each of said first and second transistors comprises: a) source and drain regions formed between a channel region in a substrate, said drain region being coupled to said corresponding bitline and said source being coupled to said third node; b) a gate insulation film formed over said channel region; and c) a gate electrode formed on said gate insulation film, wherein said controlling means comprises d) a conductive layer insulatively overlapping said gate electrode and a predetermined portion of said source region, and coupled to an exposed portion of said source region.
4.
The memory device of claim 3, wherein said source region comprises: a first region having a first predetermined concentration of n- which is partially overlapped by said gate electrode; and a second region having a second predetermined concentration of n+ coupled to said corresponding bitline.
5.
The memory device of claim 4, wherein said second predetermined concentration is larger than said first predetermined concentration.
6.
The memory device of claim 3, wherein said drain region comprises: a first region having a first predetermined concentration of n
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I/O Systems 
