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Semiconductor memory device having hierarchical bit line structure employing improved bit line precharging system
| Details |
Inventors: Tsukude, Masaki; Tsuruda, Takahiro;
Assignee: Mitsubishi Denki Kabushiki Kaisha (Tokyo, JP)
Primary Examiner: Nguyen; Viet Q.
Assistant Examiner:
Attorney, Agent or Firm: Lowe, Price, LeBlanc & Becker
A semiconductor memory device comprises a main bit line pair, a plurality of subbit line pairs, a plurality of selection transistor pairs, a plurality of word lines, a plurality of memory cells, and a plurality of first precharging circuits. The subbit line pairs are provided in correspondence to the main bit line pair. One and other subbit lines of the subbit line pairs are arranged in straight lines along the main bit line pair. The selection transistors are provided in correspondence to the subbit line pairs. Each of the selection transistor pairs is connected between the main bit line pair and the corresponding subbit line pair, and turned on in response to a prescribed selection signal. The word lines are arranged to intersect with one and the other subbit lines of the subbit line pairs. The memory cells are provided in correspondence to intersection points between one and the other subbit lines of the subbit line pairs and the word lines. Each of the memory cells is connected to the corresponding subbit line and the corresponding word line. The first precharging circuits are provided in correspondence to the subbit line pairs. Each of the first precharging circuits directly precharges the corresponding subbit line pair at the prescribed precharging potential. |
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DETAILED DESCRIPTION Accordingly, a first object of the present invention is to provide a semiconductor memory device of a hierarchical bit line structure having a high read rate.
Another object of the present invention is to provide a semiconductor memory device of a hierarchical bit line structure which can precharge subbit line pairs at a high speed.
Still another object of the present invention is to provide a semiconductor memory device which can maintain potentials of subbit line pairs at a prescribed precharging potential up to an instance immediately before data reading.
A further object of the present invention is to provide a semiconductor memory device which can precharge subbit line pairs at a high speed without increasing the chip area.
A semiconductor memory device according to a first aspect of the present invention comprises a main bit line pair, a plurality of subbit line pairs, a plurality of selection transistor pairs, a plurality of word lines, a plurality of memory cells, and a plurality of first precharging circuits.
The plurality of subbit line pairs are provided in correspondence to the main bit line pair.
First and second subbit lines of the plurality of subbit line pairs are arranged in straight lines along the main bit line pair.
The plurality of selection transistor pairs are provided in correspondence to the plurality of subbit line pairs.
Each of the plurality of selection transistor pairs is provided between the main bit line pair and the corresponding subbit line pair, and enters a conducting state in response to a prescribed selection signal.
The plurality of word lines are arranged to intersect with the first and second subbit lines of the plurality of subbit line pairs.
The plurality of memory cells are provided in correspondence to intersection points between the first and second subbit lines of the plurality of subbit line pairs and the plurality of word lines.
Each of the plurality of memory cells is connected to the corresponding subbit line and the corresponding word line
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I/O Systems 
