Semiconductor memory device incorporating a test mode therein to perform an automatic refresh function

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, explanation will be made as to the embodiment of the semiconductor memory device employing a test mode performing an automatic refresh function according to the present invention with reference to appended drawings.
FIG.
1 is a block diagram illustrating an embodiment, in which the present invention is applied to a DRAM.
The DRAM shown in FIG.
1 employs an automatic refresh circuit 100 incorporating a test mode therein.
The automatic refresh circuit 100 outputs an address signal transferred through an address input terminal to a row address pre-decoder 200 and a column address predecoder 210, and also outputs a refresh address to the row address pre-decoder 200 and the column address predecoder 210 as well when an automatic refresh operation is instructed by a row address strobe signal and a column address signal (hereinafter referred as RAS and CAS, respectively) transferred through a control signal input terminal.
The automatic refresh circuit 100 further outputs the refresh address on the address input terminal when a test mode selection signal is input which tests whether or not the automatic refresh function is correctly operated.
FIG.
2 is a block diagram of the automatic refresh circuit 100 shown in FIG.
1.
A circuit 100 incorporates therein an external input terminal 101 through which a RAS is provided and an external input terminal 103 through which CAS is provided.
RAS provided through the external input terminal 101 is input to an input circuit 105.
The input circuit 105 outputs an output signal in response to RAS to an automatic refresh control circuit 107.
CAS provided through the external input terminal 103 is input to an input circuit 109.
The input circuit 109 outputs an output signal in response to CAS to the automatic refresh control circuit 107 and a timing generation circuit 230 for internal operation (see FIG.
1).
The automatic refresh control circuit 107 outputs a control signal through a node N1 in response to the output signals from the input circuits 105 and 109 to an oscillation circuit 111 and an address signal input circuit 119, whereby the automatic refresh function is initiated