Semiconductor storage device with redundancy arrangement

DETAILED DESCRIPTION axi' An object of this invention is to shorten an access time in a semiconductor storage device provided with a redundancy circuit.
The aforesaid object and other objects of this invention and new characteristic features thereof will be apparent from the description of the present specification and the drawings annexed thereto.
The typical features of a representative embodiment of the invention disclosed in the present application will be summarized in the following.
An output of the address buffer is connected with a relatively heavy load comprised of a relatively long connecting wiring line and an address decoder.
Therefore the address buffer is designed so that the load driving ability of the final stage thereof is large.
In contrast therewith, the internal address signals supplied to the address comparator circuit can be formed by a circuit which does not require so large a driving ability.
Taking this fact into account, the present invention attains the aforesaid object of increasing the memory speed by a system wherein an address signal to be supplied to the address comparator circuit is output from a preceeding stage of the address buffer comprised with a multi-stage amplifier circuit.
Thus, the output timing of a discrimination signal output from an address comparator circuit is expedited.