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Details
Inventors: Tayler, Gerald E.; Wagner, Robert E.;
Assignee: International Business Machines Corporation (Armonk, NY)
Primary Examiner: Shaw; Gareth D.
Assistant Examiner: Mills; John G.
Attorney, Agent or Firm: Somermeyer; Herbert F.

The disclosure relates to sequential performance of a cached data storage subsystem with a minimal control signal processing. Sequential access is first detected by monitoring and examining the quantity of data accessed per unit of data storage (track) across a set of contiguously addressable tracks. Since the occupancy of the data in the cache is usually time limited, this examination provides an indication of the rate of sequential processing for a data set, i.e., a data set is being processed usually in contiguously addressable data storage units of a data storage system. Based upon the examination of a group of the tracks in a cache, the amount of data to be promoted to the cache from a backing store in anticipation of future host processor references is optimized. A promotion factor is calculated by combining the access extents monitored in the individual data storage areas and is expressed in a number of tracks units to be promoted. The examination of the group of tracks units and the implementation of the data promotion and demotion (early cast-out) is synchronized which results in a synergistic effect for increasing throughput of the cache for sequentially-processed data. A limit of promotion is determined to create a window of sequential data processing.

DETAILED DESCRIPTION Referring now more particularly to the appended drawings, like numerals indicate like features in the various figures.
Referring more particularly to FIG.
1, the environment in which the invention is practiced is described.
One or more host processors are connected to the illustrated data storage subsystem via an attachment or channel 10.
The data storage subsystem includes one or more data storage devices 11, preferably disk recorders also referred to as direct access storage devices (DASD).
A programmed control 12 in the peripheral data storage subsystem controls the subsystem operations and the transfer of data between DASD 11 and host processors through attachment 10.
Line 13 indicates this control function, which is well known.
Programmed control 12 has its own microprocessor (not shown), such as seen in U.
S.
Pat.
No.
4,466,059.
Particularly refer to FIG.
2 of the cited patent which shows the hardware arrangement which may be advantageously employed with the present invention.
Programmed control 12 has its own control program storage which includes a set of control programs (pgms) 14.
The microprocessor in programmed control 12 reads the control programs and responds thereto for effecting control and management of the data storage subsystem as represented by line 13.
The operation and management also requires a set of control tables 15 which store control commands and other parameters received from the host processors, status information about the data storage subsystem, as well as other parameters useful for operating a data storage subsystem, all as is known.
To enhance the performance of the data storage subsystem, a cache 17 is logically and electrically interposed between DASD 11 and the attachment 10.
Operation of a cache 17 is also described in the documents incorporated by reference.
Programmed control 12 has additional control programs named sequential programs (seq pgms) 24 for managing the cache as well as controlling the DASD 11 in accordance with the present invention



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