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Data output buffer control circuit of a synchronous semiconductor memory device
It is, therefore, an object of the present invention to enable a data output buffer control apparatus of a synchronous semiconductor memory device to operate in ...
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Self-regulating clock generator
The invention therefore provides a clock generator for providing an output clock signal for clocking a microprocessor having first and second speed paths requiring first ...
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Data processor having wait state control unit
Therefore, an object of the present invention is to provide a data processor having an improved wait state control circuit. Another object of the present invention is to ...
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Multiple mode memory module
OF THE INVENTION Referring first to FIG. 1 there is shown in block diagram form a portion of an information processing system 10. System 10 includes a system bus 12 ...
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System for loading initial program loader routine into secondary computer without bootstrap ROM
What is claimed is: 1. Circuit apparatus for executing an initial program loader routine from a secondary computer connected via a shared random-access volatile memory ...
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Reversible computer apparatus and methods of constructing and utilizing same
The invention provides a reversible computer apparatus capable of executing instructions in both a forward execution mode and a reverse execution mode, and includes a ...
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Full duplex buffer management and apparatus
The present invention provides for a buffer management system to dynamically allocate priority between two buffer memories, a receive memory and a transmit memory, when ...
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Dynamic storage synchronizer using variable oscillator and FIFO buffer
The present invention adds a variable rate oscillator and a FIFO buffer to a dynamic storage subsystem based upon CCD or an analogous technology. The rate at which the ...
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Token-based serialisation of instructions in a multiprocessor system
It is the task of the invention to provide a process for the serialisation of instructions in a multiprocessor system. In this case, the need to serialise specified ...
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Method and apparatus for transferring data in parallel from a smaller to a larger register
OF THE DRAWING Referring to FIG. 1, there is provided in a prior known apparatus for transferring data in parallel from a smaller to a larger register designated ...
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