 Re-configurable block length cache |
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| Detecting the presence of a device on a computer system bus by altering the bus termination |
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| Conversion of multilevel digital data to binary data |
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| Data storage buffer system and method |
| The problems with the methodologies discussed above have been alleviated by the present invention. I... |
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| Binary input processing in a computer using a stack |
| With reference now to the drawing, it may be seen that the various blocks depicted therein are ... |
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| Circuit for designating instruction pointers for use by a processor decoder |
| FIG. 2 schematically illustrates an instruction pointer designation circuit 200 in accordance with ... |
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| Methods and apparatus for translating incompatible bus transactions |
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| Data-array processing system wherein parallel processors access to the memory system is optimized |
| OF THE PREFERRED EMBODIMENTS Preferred embodiments of the invention will now be described, by way ... |
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| Video signal memories |
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Single chip remote access processor
| Details |
Inventors: Kumar, Shailendra; Sonnek, Christopher D.;
Assignee: LSI Logic Corporation (Milpitas, CA)
Primary Examiner: Patel; Ajit
Assistant Examiner: Pizarro; Ricardo M.
Attorney, Agent or Firm: Westman, Champlin & Kelly, P.A.
A single chip integrated remote access processor circuit has a plurality of communication interface units, including a local area network (LAN) interface unit, a first multi-protocol serial wide area network (SWAN) interface unit, a telephony coder-decoder interface unit and a peripheral component interface (PCI) unit. A data routing control circuit is coupled to the plurality of communication interface units for controlling data transfer between the interface units. |
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DETAILED DESCRIPTION The single chip integrated remote access processor of the present invention has a plurality of communication interface units, including a local area network (LAN) interface unit, a first multi-protocol serial wide area network (SWAN) interface unit, a telephony coder-decoder interface unit and a peripheral component interface (PCI) unit.
A data routing control circuit is coupled to the plurality of communication interface units for controlling data transfer between the interface units.
In one embodiment, the data routing control circuit includes an internal transfer bus, a multi-channel direct memory access (DMA) controller, a central processing unit (CPU), an internal memory, a local memory interface, a local memory controller and a bridge circuit.
The internal transfer bus is coupled to the DMA controller, CPU, local memory controller and bridge circuit for passing data, address and control information to and from the various elements.
The DMA controller has a first channel coupled to the LAN interface unit, a second channel coupled to the multi-protocol SWAN interface unit and a third channel coupled to the telephony coder-decoder interface unit.
The internal memory is coupled to the DMA controller and the CPU for maintaining buffer memory descriptor lists for each DMA channel.
The local memory controller is coupled between the internal transfer bus and the local memory interface for storing data packets received at one of the communication interfaces in an external local memory and then retrieving the data packets for transmission through one or more of the other communication interfaces, under the control of the CPU.
The bridge circuit is coupled between the PCI interface unit and the local memory controller for transferring data packets between the PCI interface unit and the local memory.
The single chip integration enables high performance and low cost.
A scalable CPU and a fast local memory interface creates a robust programmable platform for end users to customize their applications
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I/O Systems 
