 Apparatus and method for reading helically recorded tracks and rereading tracks as necessary |
| OF THE DRAWINGS A helical-scan drive system 10 for recording on and reading magnetic tape 12 is ... |
|
| Method of compactly storing digital data |
| This invention provides a method of storing digital data in a compact manner which includes the ... |
|
| Universal device for coupling a computer bus to a controller of a group of peripherals |
| We claim: 1. A universal device for coupling a computer bus of a computer to a controller of a ... |
|
| Monitoring plural process control stations |
| We claim: 1. A monitoring system for process controllers with error recognition and compensation in ... |
|
| Arbitration circuitry for deciding access requests from a multiplicity of components |
| We claim: 1. In a data-handling system with a multiplicity n=2.sup.m of components of different ... |
|
|
Split bus multiprocessing system with data transfer between main memory and caches using interleaving of sub-operations on sub-busses
| Details |
Inventors: Shaffer, Stephen J.; Warren, Richard A.; Eggers, Thomas W.; Strecker, William D.;
Assignee: Digital Equipment Corporation (Maynard, MA)
Primary Examiner: Williams, Jr.; Archie E.
Assistant Examiner: Mohamed; Ayni
Attorney, Agent or Firm: Holloway; William W., Gunther; John M.
In a data processing system in which a plurality of data processing units, as well as the main memory unit, are coupled to a system bus, the utilization of the system bus can be increased to such an extent that each of a plurality of cache memory units coupled to the system bus can have a plurality of data processing units coupled thereto. The system bus utilization is increased by dividing the system bus access operation into a plurality of sub-operations and by providing a defined cyclic sequence for the cache memory units to have access to the system bus. The system bus is divided into a plurality of sub-bus units to handle separate functions of data transfer. The main memory unit has apparatus for efficient execution of the write-modify-read operation. In addition, the cache memory units can be divided in a plurality of sub-units and the access to the system bus arranged in terms of cyclic access of the cache memory subunits. |
|
DETAILED DESCRIPTION It is therefore an object of the present invention to provide an improved data processing system.
It is another object of the present invention to provide an improved data processing system having a plurality of data processing units.
It is yet another object of the present invention to provide improved performance of a multi-processing unit data processing system utilizing a system bus.
It is a particular object of the present invention to provide an improved system bus implementation for use with a data processing system.
It is another more particular object of the present invention to provide an improved data processing system in which a plurality of data processing units can store a given data signal group.
It is another particular object of the present invention to provide, in a data processing system, a system bus for which an access operation is divided into a plurality of sub-operations.
It is yet another particular object of the present invention to provide a system bus in which access to the system bus by the plurality of data processing units utilizes multiplexing techniques.
It is a further object of the present invention to provide a system bus in which access to the system bus is multiplexed with respect to a plurality of address signal sub-groups related to each data processing unit's cache memory unit.
It is still another object of the present invention to provide a data processing system having a plurality of cache memory units coupled to the system bus, wherein each cache memory unit can have a plurality of data processing units coupled thereto.
It is a particular object of the present invention to provide a data processing system in which a system bus utilizes both multiplexing and pipelining techniques.
It is still another particular object of the present invention to provide a data processing system for which access to a system bus by data processing and units uses multiplexing and pipelining techniques, and wherein a plurality of cache memory units are coupled to the system bus and capable of having a plurality of data processing units coupled to each cache memory unit
|
| Related patents |
|
|
Memory access control circuit with automatic access mode determination circuitry with read-modify-write and write-per-bit operations
Therefore, an object of the present invention is to provide a memory access control circuit which determines an optimum memory access mode and performs the determined ...
|
|
|
Data driven information processing system using address translation table to keep coherent cache and main memories and permitting parallel readings and writings
Therefore, an object of the present invention is to provide a data driven information processing system allowing accurate read/write from and to the memory at high speed ...
|
|
|
Cache memory having a read-modify-write operation and simultaneous burst read and write operations and a method therefor
Accordingly, there is provided, in one form, a cache memory having a plurality of memory cells, a word line decoding circuit, and column decoding logic. The word line ...
|
|
|
Apparatus and method for providing a transparent disk drive back-up
OF THE PREFERRED EMBODIMENT Having summarized various aspects of the present invention, reference will now be made in detail to the description of the invention as ...
|
|
|
Method for preventing unauthorized modification of data in a device with a nonvolatile memory
It is accordingly an object of the invention to provide a method for preventing unauthorized data modification in a device with a nonvolatile memory, which overcomes the ...
|
|
|
Method of reading digital data on magnetic tape
I have hereby invented how to read digital data written in the standard format on a magnetic tape, more quickly than heretofore in the face of possible errors that will ...
|
|
|
Method and apparatus for synchronizing disk drive requests within a disk array
There is provided, in accordance with the present invention, a method and apparatus for generating a single request signal for a logical storage unit including all or a ...
|
|
|
Method and apparatus for an enhanced computer system interface
It is therefore an object of the present invention to provide an improved interface, based in part on the proposed SCSI-2 standard, by which multiple-byte commands, ...
|
|
|
Data processing device having an expandable address space
In the aforementioned CPU, however, the address register has a length of 16 bits, and the memory to be referred to by the CPU has a capacity of 65,536 bytes (=2.sup.16 ...
|
|
|
Single-chip mircocomputer with clock-signal switching function which can disable a high-speed oscillator to reduce power consumption
It is, therefore, an object of the present invention to overcome the problem existing in the conventional arrangement and to provide an improved single-chip ...
|
|
|
I/O Systems 
