Circuit for designating instruction pointers for use by a processor decoder |
| FIG. 2 schematically illustrates an instruction pointer designation circuit 200 in accordance with ... |
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Methods and apparatus for translating incompatible bus transactions |
| Circuit arrangements and methods are disclosed for upgrading an 040-based personal computer system ... |
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Data-array processing system wherein parallel processors access to the memory system is optimized |
| OF THE PREFERRED EMBODIMENTS Preferred embodiments of the invention will now be described, by way ... |
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Video signal memories |
| One object of the present invention is to provide a video signal memory in which data can be ... |
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Obtaining access to a two-dimensional portion of a digital picture signal |
| The invention provides a method of obtaining access to a two-dimensional portion of a digital ... |
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Devices, systems and methods for accessing data using a pixel preferred data organization |
| According to the invention, a processing system is provided operating on data words each having at ... |
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Display apparatus |
| The present invention has been attempted to solve the above-described problems, and therefore, has ... |
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Video timing and display ID generator |
| The invention provides an improved video timing generator and display ID generator that function at ... |
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Digital recorder for processing in parallel data stored in multiple tracks |
| It is therefore an object of the present invention to provide a digital recorder which is designed ... |
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Stack caching method with overflow/underflow control using pointers
| Details |
Inventors: Koppala, Sailendra;
Assignee: Sun Microsystems, Inc. (Palo Alto, CA)
Primary Examiner: Peikari; B. James
Assistant Examiner:
Attorney, Agent or Firm: Gunnison; Forrest
The present invention uses a stack management unit including a stack cache to accelerate data retrieval from a stack and data storage into the stack. In one embodiment, the stack management unit includes a stack cache, a dribble manager unit, and a stack control unit. The dribble manager unit maintains a cached stack portion, typically a top portion of the stack in the stack cache. The stack cache includes a stack cache memory circuit, one or more read ports, and one or more write ports. The stack management unit also includes an overflow/underflow unit. The overflow/underflow unit detects and resolves overflow conditions and underflow conditions. If an overflow occurs the overflow/underflow unit resolves the overflow by suspending operation of the stack cache and spilling a plurality of data words from the stack cache to the stack and equating the bottom pointer to the optop pointer. Typically, the overflow/underflow unit spills all valid data words from the stack cache during an overflow. If an underflow occurs during a context switch the overflow/underflow unit resolves the underflow by spilling a plurality of data word from the stack cache to the stack and equating the bottom pointer to the optop pointer. If an underflow without a context switch the overflow/underflow unit resolves the underflow by equating the bottom pointer to the optop pointer. |
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DETAILED DESCRIPTION Accordingly, the present invention provides a stack management unit including a stack cache to accelerate data retrieval from a stack and data storage into the stack. In one embodiment, the stack management unit includes a stack cache, a dribble manager unit, and a stack control unit. The dribble manager unit maintains a cached stack portion, typically a top portion of the stack in the stack cache. Specifically, when the stack-based computing system is pushing data onto the stack and the stack cache is almost full, the dribble manager unit transfers data from the bottom of the stack cache to the stack. When the stack-based computing system is popping data off the stack and the stack cache is becoming empty, the dribble manager unit transfers data from the stack to the bottom of the stack cache. The stack cache includes a stack cache memory circuit, one or more read ports, and one or more write ports. The stack cache memory circuit contains a plurality of memory locations, each of which can contain one data word. In one embodiment the stack cache memory circuit is a register file configured with a circular buffer memory architecture. For the circular buffer architecture, the registers can be addressed using modulo addressing. Typically, an optop pointer is used to define and point to the first free memory location in the stack cache memory circuit and a bottom pointer is used to define and point to the bottom memory location in the stack cache memory circuit. As data words are pushed onto or popped off the stack, the optop pointer is incremented or decremented, respectively. Similarly, as data words are spilled or filled between the stack cache memory circuit and the stack, the bottom pointer is incremented or decremented, respectively. Some embodiments of the stack management unit include an overflow/underflow unit. The overflow/underflow unit detects and resolves overflow conditions, i. e. , when the number of used data words required in the stack cache exceeds a overflow threshold or the capacity of the stack cache, and underflow conditions, i
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