Dynamic random access memory arrangements having WE, RAS, and CAS derived from a single system clock |
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Power saving sense amplifier that mimics non-toggling bitline states |
| According to the invention, a sense amplifier selectively prevents formation of the current branch ... |
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Communication multiplexer sharing a free running timer among multiple communication lines |
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Data output buffer control circuit of a synchronous semiconductor memory device |
| It is, therefore, an object of the present invention to enable a data output buffer control ... |
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Self-regulating clock generator |
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Data processor having wait state control unit |
| Therefore, an object of the present invention is to provide a data processor having an improved ... |
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Synchronization and error detection in a packetized data stream
| Details |
Inventors: Heegard, Chris; King, Andrew J.; Lovely, Sydney; Kolze, Thomas J.;
Assignee: General Instrument Corporation of Delaware (Chicago, IL)
Primary Examiner: Baker; Stephen M.
Assistant Examiner:
Attorney, Agent or Firm: Lipsitz; Barry R., Hoppin; Ralph F.
A method and apparatus are provided for achieving synchronization and detecting errors in a data stream such as an MPEG-2 transport packet stream. In an MPEG embodiment, the MPEG sync word is removed and replaced with a parity code that is used at the decoder for both synchronization and error detection. A syndrome calculator in the decoder can be implemented using a unique one bit in, one bit out FIR filter. Codewords used to generate the parity code can be provided by a linear block code that is a dual of a shortened cyclic code. |
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DETAILED DESCRIPTION In accordance with the present invention, a method is provided for achieving synchronization and detecting errors in a data stream carrying successive packets of k information bits and r synchronization bits. The synchronization bits of each packet comprise a predefined, searchable pattern. At least one synchronization pattern is located in the data stream to enable the boundaries for the k information bits of successive packets to be determined. In one embodiment, the synchronization pattern in each packet is replaced with an r-bit parity code derived from a counterpart set of k information bits in the data stream, thereby generating a modified data stream. The modified data stream is communicated to a decoder. At least one of the parity codes is located in the modified data stream at the decoder to achieve synchronization. This enables the boundaries for the k information bits of successive packets to be determined. Once synchronization has been achieved, the parity codes are compared to checksums obtained from their counterpart k information bits at the decoder to determine when the information bits in a received packet contain an error. The data stream can comprise an MPEG compatible data stream, e. g. , an MPEG-2 data stream or a similarly formatted data stream. The parity codes can be scaled such that when decoded at the decoder, they will match MPEG synchronization patterns. In an MPEG-2 embodiment, the number of information bits (prefix, adaptation field and payload) in a packet is k=1496. In a preferred MPEG implementation, the synchronization pattern for each packet precedes the k information bits of that packet, whereas the counterpart set of k information bits for each parity code comprises the k information bits immediately preceding the parity code. The parity code can be generated from a linear block code comprising a dual of a shortened cyclic code. Communication apparatus in accordance with the present invention enables a receiver to robustly obtain synchronization and detect errors in a data stream carrying successive packets of k information bits and an r-bit parity code
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