Home | Links | Contact Us | More About Intellectual Property | Bookmark
Search patents:
Home I/O Systems Synchronization-of-time-of-day-clocks-in-a-distributed-processing-network-system

 Media connect module for portable computer
The present invention is directed to a module which may be connected to an I/O port of a notebook ...


 Initializing a read pipeline of a non-volatile sequential memory device
A sequential memory device having a read pipeline data structure is provided that is initialized ...


 Data read circuit for use in semiconductor storage apparatus of CMOS memory
An essential object of the present invention is to provide a data read circuit for use in a ...


 Data communications system with improved asynchronous retiming circuit
The present invention relates to an improved asynchronous data communications system including a ...


 Line driver circuit
Accordingly, an object of the present invention is to provide a line driver circuit which can ...


 Non-coherent pattern detection
The present invention is directed to a digital non-coherent pattern detection scheme in which ...


 Decoder for three level coded data
Accordingly, it is an object of the invention to provide improved means for converting a three ...


 Time-division multiplex communication transmission apparatus
It is an object of the present invention to provide a time-division multiplex radio transmission ...


 Transmitted reference spread spectrum communications system
One object of the invention is to provide a simple and inexpensive method and apparatus for ...


 Image display apparatus
It is an object of the present invention to provide an image display apparatus which can solve the ...


 Synchronization of time-of-day clocks in a distributed processing network system

Details
Inventors: Edblad, Warren A.; Crew, Albert W.; Staab, Carl J.;
Assignee: Westinghouse Electric Corp. (Pittsburgh, PA)
Primary Examiner: Chin; Stephen
Assistant Examiner: Le; Amanda T.
Attorney, Agent or Firm: Watkins; P. C.

The operating system clocks in each station on a counter rotating ring network of a distributed processing system are synchronized by latching the count in a free running counter in the network interface of each station at the instant a clock message transmitted by a timekeeper station is received. The timekeeper station then calculates from its operating system time-of-day clock and its free running counter, its time of reception of the clock message, and broadcasts this timekeeper time of reception to the other stations. Each other station calculates its own time of reception from its operating system time of day, and the count in its free running counter, and uses the difference between its time of reception and the timekeeper time of reception to correct its operating system time-of-day clock. Repeater and media propagation delays determined from the dynamic topography of the network are taken into account in calculating the correction factor. The free running counter can also be used to maintain a higher resolution local time of day than is available from the operating system time-of-day clock.

DETAILED DESCRIPTION It is an object of the present invention to provide improved means for synchronizing station time-of-day clocks in a distributed processing system.
It is another object of the invention to achieve this primary object with minimum specialized hardware.
It is an additional object of the invention to achieve the previous objects utilizing each station's operating system time-of-day clock, and to do so even when the operating system time-of-day clock does not have the resolution demanded by the network system.
It is also an object of the invention to provide such an improved means for synchronizing station time-of-day clocks which accommodates for network delays and for dynamic changes in the network delays, such as would accompany changes in network topography.
These and other objects are realized by the invention which is directed to a distributed processing system with means for synchronization of station time-of-day clocks which includes in each station a free-running counter in the network interface which maintains a count of time intervals.
It further includes means within a designated timekeeper station periodically generating a timing signal which is transmitted over the data communications network to all of the stations including the timekeeper station.
Means in each network interface latches the count in the free-running counter upon receipt of the timing signal.
The timekeeper station further includes means transmitting to all the stations the timekeeper time-of-day signal representing the time of day that the time the timekeeper station received the timing signal.
Each of the other stations include means determining a station reference time of day from the latched count, and the count in the free-running counter, and from the time of day in the operating system time-of-day clock at the time of receipt of the timekeeper time-of-day signal.
Each station further includes means determining the difference between the station reference time of day and the received timekeeper time of day and adjusting the time of day clock in the operating system based on this difference



Related patents
  Information transfer system
The present invention is an information transfer system which transfers altered or new information to a selected one of a plurality of circuit stages via a data without ...
  Semiconductor memory device
An object of the present invention is to allow high speed access operation in a semiconductor memory device including a plurality of memory cell regions without increase ...
  Programmable memory controller for power and noise reduction
In accordance with the present invention, there is provided an apparatus for providing memory address and control signals to single in-line memory module (SIMM) ...
  Layout of a semiconductor memory device
An object of the present invention is to ensure proper operation of a sense amplifier, and to reduce sensing time and improve sensitivity thereof. Another object of the ...
  Integrated circuit module having on-chip surge capacitors
In accordance with the present invention, capacitance filtering is provided for a circuit having an array of similar semiconductor circuit devices, such as a SIMM (...
  Floating gate nonvolatile memory with distributed blocking feature
FIG. 2 illustrates in block diagram form the physical die layout of a flash EPROM 50, which implements a preferred embodiment of the present invention. Flash EPROM 50 ...
  Dram wtih open digit lines and array edge reference sensing
The above mentioned problems with integrated memories and other problems are addressed by the present invention and which will be understood by reading and studying the ...
  Method of and circuitry for generating staggered restore timing signals in block partitioned DRAM
An object of the present invention is to solve the above described problems and to provide a dynamic type semiconductor memory device capable of reducing peak current ...
  Dynamic logic having power-down mode with periodic clock refresh for a low-power graphics controller
A controller chip has dynamic logic which is driven by a suspendable clock. Power is reduced in a standby mode when the clock to the dynamic logic is stopped. However, ...
  Timing apparatus and timing method for wrapper cell speed path testing of embedded cores within an integrated circuit
What is claimed is: 1. An integrated circuit comprising: an embedded core which is adapted to receive a first clock; a plurality of test cells coupled to one or more ...

0.044

Archive: All patents - Links

Copyright (c)2006 Eipa-patents.org - All rights reserved