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Information transfer system
The present invention is an information transfer system which transfers altered or new information to a selected one of a plurality of circuit stages via a data without ...
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Semiconductor memory device
An object of the present invention is to allow high speed access operation in a semiconductor memory device including a plurality of memory cell regions without increase ...
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Programmable memory controller for power and noise reduction
In accordance with the present invention, there is provided an apparatus for providing memory address and control signals to single in-line memory module (SIMM) ...
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Layout of a semiconductor memory device
An object of the present invention is to ensure proper operation of a sense amplifier, and to reduce sensing time and improve sensitivity thereof. Another object of the ...
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Integrated circuit module having on-chip surge capacitors
In accordance with the present invention, capacitance filtering is provided for a circuit having an array of similar semiconductor circuit devices, such as a SIMM (...
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Floating gate nonvolatile memory with distributed blocking feature
FIG. 2 illustrates in block diagram form the physical die layout of a flash EPROM 50, which implements a preferred embodiment of the present invention. Flash EPROM 50 ...
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Dram wtih open digit lines and array edge reference sensing
The above mentioned problems with integrated memories and other problems are addressed by the present invention and which will be understood by reading and studying the ...
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Method of and circuitry for generating staggered restore timing signals in block partitioned DRAM
An object of the present invention is to solve the above described problems and to provide a dynamic type semiconductor memory device capable of reducing peak current ...
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Dynamic logic having power-down mode with periodic clock refresh for a low-power graphics controller
A controller chip has dynamic logic which is driven by a suspendable clock. Power is reduced in a standby mode when the clock to the dynamic logic is stopped. However, ...
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Timing apparatus and timing method for wrapper cell speed path testing of embedded cores within an integrated circuit
What is claimed is: 1. An integrated circuit comprising: an embedded core which is adapted to receive a first clock; a plurality of test cells coupled to one or more ...
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