 High-speed synchronous write control scheme |
| A semiconductor memory device having pairs of data lines for reading and writing data signals to ... |
|
| Elasticity buffer for data/clock synchronization |
| OF PREFERRED EMBODIMENT The present invention has application to any data transfer system that ... |
|
| Computer systems and methods for pipelined transfer of data between modules |
| Synchronous Global Bus The chief object of the present invention is to perform fast block transfers ... |
|
| Dynamic random access memory system |
| It is object of the present invention to minimize the number of address control pins and signal ... |
|
| Optical clock distribution system |
| OF THE PREFERRED EMBODIMENT In the following detailed description of the preferred embodiment, ... |
|
| Modular bus with single or double parallel termination |
| Single Channel Bus In one embodiment of a modular single channel bus architecture, a master bus ... |
|
| Memory controller with low skew control signal |
| OF THE PREFERRED EMBODIMENTS Prior to discussing the preferred embodiments of the invention, a ... |
|
| Backup method and apparatus allowing only replaced data to be transferred |
| This invention aims at enhancing efficiency in utilizing a communications link by shortening a data ... |
|
| Integratable, bus-oriented transmission system |
| It is an object of the invention to increase the switching speed given a data transmission system ... |
|
|
Synchronous semiconductor memory device
| Details |
Inventors: Iwamoto, Hisashi; Konishi, Yasuhiro; Dosaka, Katsumi; Murai, Yasumitsu;
Assignee: Mitsubishi Denki Kabushiki Kaisha (Tokyo, JP)
Primary Examiner: Nelms; David C.
Assistant Examiner: Le; Vu A.
Attorney, Agent or Firm: Lowe, Price, LeBlanc & Becker
To one memory array, global signal input/output line pairs in two systems, a switch for connecting the global IO line pairs to a write buffer group alternately on a clock cycle basis, and another switch for connecting the global IO line pairs to an equalize circuit alternately on a clock cycle basis are provided. During one clock cycle, writing of data through one global IO line pair and equalization of the other global IO line pair can be carried out in parallel. Therefore, data can be written easily at a high frequency. |
|
DETAILED DESCRIPTION The principal object of the present invention is to provide a synchronous semiconductor memory device enabling high speed operation and random writing.
Briefly speaking, in a first synchronous semiconductor memory device according to the present invention, each of memory cells continuously selected by a selection circuit is alternately connected to first and second signal input/output line pairs on a clock cycle basis.
Therefore, data can be written through one signal input/output line pair during one clock cycle, and the other signal input/output line pair may be equalized during the one clock cycle.
As a result, data can be written easily at a high frequency, as compared to a conventional case in which data is written through one signal input/output line pair during one clock cycle, and the signal input/output line pair is equalized.
Further, random writing can be carried out.
A data input/output circuit includes a data writing circuit and an equalize circuit.
While the data writing circuit writes data through one signal input/output line pair, the equalize circuit equalizes the other signal input/output line pair.
As a result, the data input/output circuit is easily structured.
The data input/output circuit includes first and second data writing circuits and an equalize circuit.
While the first data writing circuit writes data through the first signal input/output line pair, the equalize circuit equalizes the second signal input/output line pair.
While the second data writing circuit writes data through the second signal input/output line pair, the equalize circuit equalizes the first signal input/output line pair.
As a result, the data input/output circuit is easily structured.
In brief, in a second synchronous semiconductor memory device according to the present invention, each of memory cell pairs continuously selected by a selection circuit is connected to first and second signal input/output line pairs.
Data of two bits are written at a time in a memory cell pair in the first two clock cycles in which a write time is shortened due to generation of an internal address signal, and then data of one bit is written alternately in one and the other memory cells in a memory cell pair on a clock cycle basis
|
|
I/O Systems 
