Synchronous semiconductor memory device operable in a plurality of data write operation modes

DETAILED DESCRIPTION An object of the invention is to provide an SDRAM which allows easy adjustment of an internal data transfer mode in accordance with a clock to be used.
Another object of the invention is to provide an SDRAM in which an internal data transfer mode can be easily set in accordance with an operation environment for use without an awareness by a user.
Yet another object of the invention is provide an SDRAM which is user-friendly, and allows easy management by a manufacturer.
Briefly, a synchronous semiconductor memory device according to the invention has a structure, in which a write data transfer method can be set to either a pipelined mode or a multibit prefetch mode in accordance with data stored in a mode register storing data designating an operation mode of the synchronous semiconductor memory device.
A synchronous semiconductor memory device according to the invention includes a memory array having a plurality of memory cells, an internal clock generating circuit for receiving an externally applied external clock signal, and generating an internal clock signal determining a data write cycle in synchronization with the external clock signal, and a data write circuit for writing data into a selected memory cell in the memory array in synchronization with the internal clock signal during data writing.
The data write circuit is operable in a pipelined mode for writing different data into the different memory cells every cycle of the internal clock signal and a prefetch mode for writing different data into the plurality of memory cells every multiple cycles of the internal clock signal.
The synchronous semiconductor memory device according to the invention further includes a mode register for storing data related to an operation speed of the semiconductor memory device, and a mode setting circuit for setting the operation mode of the data write circuit to either the pipelined mode or the prefetch mode.
In accordance with the data related to the operation speed stored in the mode register, the mode setting circuit sets the operation mode of the data write circuit