DETAILED DESCRIPTION FIG. 1 shows a computer system 100 having a processor 110, also referred to herein as a controller 110, a cache array 120, and a data buffer 130. In use, the controller 110 receives data inputs S0, S1. As used herein, "data input" refers to any portion of the controller 110 capable of receiving data to be processed. The controller 110 attempts to store the data in the cache array 120 for processing. If the cache array 120 is full or otherwise inaccessible, then the controller 110 attempts to store the input data in the data buffer 130. The data buffer 130 has a plurality of entries, or slots, for storing incoming data. Entries in the data buffer 130 may be accessed randomly, in that data may be stored to any open slot rather than to slots in a particular order. For example, a data buffer 130 may use an address pointer (not shown) that sweeps through the entries to store data in a slot. In one embodiment, the data buffer 130 has a data field 140 that stores the data, and a valid bit 150 corresponding to each data entry. In one embodiment, the data buffer 130 may have 24 entries numbered 0 through 23. When data is written to the data buffer 130, the valid bit 150 is set for the respective data field 140, indicating that data is stored in the data field 140. The controller 110 may be instructed to write only to those entries in the data buffer 130 that are empty, as indicated by a cleared valid bit 150. When space becomes available in the cache array 120, the controller 110 removes data from a data entry in the data buffer 130 and stores it to the cache array 120. When the data is removed from the data buffer 130, the valid bit 150 corresponding to the removed data is reset, indicating that the particular data entry may be overwritten. In the embodiment shown, the controller 110 receives two data inputs S0, S1. One or both of these inputs may receive data at a given moment. Therefore, in order to receive data on the inputs S0, S1, the data buffer 130 must have at least two available entries
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