System for controlling an internally-installed cache memory

DETAILED DESCRIPTION An object of the present invention is to maintain consistency between a main memory and an internally-installed cache even when the portion of the logical address other than the offset portion is used as the set address of the cache.
A feature of the present invention resides in a cache memory control system in a computer system comprising a main memory apparatus, a plurality of data processing apparatuses with respective CPUs and a system bus connecting them.
The cache memory control system comprises a cache memory portion and a tag portion.
They are provided in said CPU and have an N-way set associative structure.
The cache uses A bits of an offset portion which is not subjected to the address translation of the logical address and a B-bit portion other than the offset portion.
The B-bit portion is subjected to an address translation.
The cache also uses an address monitor portion having a tag portion corresponding to the tag portion of the CPU using only A bits of the offset portion of the set address which are used as the set address in said CPU and having 2.
sup.
B .
times.
N-way set associative structure and means for making the tag portion of the CPU correspond to the tag portion of the address monitor portion.
Thus, it manages the N address stored in said tag portion and transmits the result of the address observation to the CPU and invalidates the corresponding recording portion of the tag in the CPU.