System for data transfer across asynchronous interface

DETAILED DESCRIPTION Briefly, the present invention includes a bridge with an input data register and multiple interface registers in one clock domain that can transfer data packets to a second clock domain.
The use of multiple interface registers in the bridge permits transferring multiple data packets between different clock domains during a single transfer cycle to enable the bridge to keep up with the disparity of data transfer rates due to the difference in clock domains.
The data packets transferred from the bridge are prioritized by size with the longer data packets being transferred first.
The shortest data packets are the last to be transferred and the data packets from different I/OPs are grouped together until the interface registers are filled and then transferred from the bridge during a single transfer cycle thus allowing the data transfer into and out of the bridge at the same rate.