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System for executing, canceling, or suspending a DMA transfer based upon internal priority comparison between a DMA transfer and an interrupt request
| Details |
Inventors: Satoh, Kohtaroh;
Assignee: NEC Corporation (Tokyo, JP)
Primary Examiner: Lee; Thomas C.
Assistant Examiner: Yuan; Chien
Attorney, Agent or Firm: Whitham, Curtis & Whitham
A data processing device having a DMA function for controlling DMA transfer, comprises a DMA unit, a CPU, a bus arbitration unit for controlling bus-using right of the DMA unit or the CPU, and an interruption controller for supplying an interruption request signal. The DMA unit includes a register, a comparator for making a comparison between a priority of a DMA transfer and a priority set on an interruption request, and a sequencer for deciding whether the DMA transfer is to be executed, canceled, or suspended in the operation state of a DMA unit according to the comparison result of the comparator. |
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DETAILED DESCRIPTION An object of the present invention is to provide a data processing device capable of shortening the processing time for stopping the DMA transfer, by stopping the DMA transfer according to the control of hardware, even in case of stopping the DMA transfer because of a higher-priority interruption request signal being issued.
Another object of the present invention is to provide a data processing device capable of decreasing the size of the control program of a data processing device by stopping the DMA transfer according to other means than software.
According to one aspect of the invention, a data processing device having a DMA function for controlling DMA transfer, comprising a DMA unit, a CPU, a bus arbitration unit for controlling bus-using right of the DMA unit or the CPU, and an interruption controller for supplying an interruption request signal, the data processing device wherein the DMA unit comprises priority comparison means for making a comparison between the priority set on the DMA unit and the priority set on the interruption request; and a DMA transfer control means for deciding the DMA transfer to be executed, canceled, or suspended in the operation state of the DMA unit according to the comparison result of the priority comparison means.
The DMA transfer control means may stop DMA transfer, so to return the DMA unit to the initial state when the priority of the interruption request occurring during the DMA transfer is higher than the priority of the DMA unit, suspend DMA transfer when the priority of the interruption request occurring during the DMA transfer is equal to the priority of the DMA unit and resumes the DMA transfer after completion of the interruption processing by the interruption request, and continue DMA transfer when the priority of the interruption request occurring during the DMA transfer is lower than the priority of the DMA unit.
The DMA transfer control means, upon receipt of an asynchronous input signal of ICE chip interruption request from external during DMA transfer, may stops the DMA transfer, so to return the DMA unit to the initial state
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I/O Systems 
