System for loading initial program loader routine into secondary computer without bootstrap ROM

DETAILED DESCRIPTION What is claimed is: 1.
Circuit apparatus for executing an initial program loader routine from a secondary computer connected via a shared random-access volatile memory to a primary computer, comprising: first means for storing the initial program loader routine in the mass memory of the primary computer; second means for copying the initial program loader routine from said mass memory into said volatile shared memory; third means for sending a restart instruction from the primary computer to a central processing unit of the secondary computer after the initial program loader has been stored in said volatile shared memory; fourth means, responsive to said restart instruction, for initially routing all program memory access instructions coming from the central processing unit of the secondary computer to the portion of the shared memory containing the initial program loader routine; fifth means for sending an acknowledge signal from the central processing unit of the secondary computer when said central processing unit has read the last instruction of the initial program loader routine out of the shared memory; a control bus linking the secondary computer central processing unit and the secondary computer program memory; a control line connecting the primary computer to the secondary computer central processing unit for applying said restart instruction; an acknowledgement line connected to the secondary computer central processing unit for providing said acknowledgement signal; and memory access logic circuit connected into the control bus at a point intermediate the central processing unit and the program memory, said memory access logic circuit further comprising a flip flop having a first input connected to said control line, a second input, a noninverting output and an inverting output, and first and second OR gates each having a pair of inputs and an output, the noninverting output and the inverting output of the flip-flop being respectively coupled to a first input of the first OR gate and to a first input of the second OR gate, the second inputs being connected to the portion of the control bus coming from the secondary computer central processing unit, the first OR gate being connected to the portion of the control bus leading to the program memory, and the output of the second OR gate being connected to the shared memory