System for transferring 32-bit double word IDE data sequentially without an intervening instruction by automatically incrementing I/O port address and translating incremented address

DETAILED DESCRIPTION In accordance with the invention, a system is provided for transferring data expressed as 32-bit words between a host personal computer operative in a 32-bit mode and an IDE peripheral storage device adapted to transfer data as 16-bit words over an ISA bus, wherein data to be transferred is stored in an addressable register in the peripheral device in response to an offset address comprising a portion of the peripheral's I/O port address.
The system comprises microprocessor means, responsive to a microprocessor input or output instruction, for transferring 32-bit data words to or from the peripheral storage device.
The microprocessor means transfers 32-bit data words from an internal 32-bit data transfer register in two sequential 16-bit words without an intervening input or output instruction.
The first word is transferred to or from the peripheral, over an ISA bus, in association with the peripheral's I/O port address including the offset address defining the addressable register.
The microprocessor means automatically increments the offset address portion associated with the second 16-bit word.
An interface adapter is coupled between the microprocessor and the IDE peripheral storage device which includes means for recognizing an incremented offset address portion of the I/O port address.
Means are also provided for translating the incremented offset address portion to the offset address defining the peripheral's addressable register.
In particular, the invention provides means for defining an alias I/O port address which corresponds to a valid I/O port address.
The microprocessor is instructed to associate the alias address with the 16-bit data words, rather than the valid I/O port address.
The microprocessor then increments the offset address portion of the alias address.
The interface adapter recognizes the port address as being an alias and translates the alias I/O port address to the valid I/O port address such that the offset address portion of both the first and second 16-bit words each corresponds to the offset address of the 16-bit data storage register