System having an address generating unit and a log comparator packaged as an integrated circuit seperate from cache log memory and cache data memory

DETAILED DESCRIPTION It is an object of the present invention to propose a computer architecture not subject to the above difficulties.
It is another object of the present invention to propose a cache-based computer architecture.
It is another object of the present invention to propose a cache-based computer architecture which minimizes chip boundary crossings.
It is another object of the present invention to propose a cache-based computer architecture in which cache data is available on the data bus even before a match is detected.
It is another object of the present invention to propose a virtual memory computer architecture with a direct mapped cache.
The above objects and others are accomplished according to the invention by integrating the tag comparator logic on the same chip as the address generating module, and disposing the cache tag and data RAMs externally to that chip.
An address translation unit may be included on the same chip as, and logically between, the address generating unit and the tag comparator logic if the computer architecture includes virtual memory.
Further, if the computer architecture separates instruction and data memory, separate instruction and data caches may be employed with interleaved bus access.