Technique for accessing and refreshing memory locations within electronic storage devices which need to be refreshed with minimum power consumption

DETAILED DESCRIPTION This and additional objectives are accomplished by the various aspects of the present invention, wherein, briefly, according to a principle aspect, memory locations within the DRAM memory structure are accessed row by row, starting with the lowest row address, in a consecutive manner such that all memory locations having the same row address within each of the DRAMs are accessed before a memory location with a higher row address within any of the DRAMs is accessed.
The result of accessing memory locations in this manner is that data is written to or read from the lowest rows of each DRAM within the DRAM memory structure before a next higher row within the DRAM memory structure is written to or read from.
Once data is written to the memory locations within the DRAM memory structure in this fashion, the present invention is then able to reduce the number of refresh cycles needed to preserve the data within the DRAM memory structure by refreshing only those rows within the structures that contain data.
This reduction in the number of refresh cycles results in a lower power consumption of the device, thereby extending the battery life of the device during a power failure.
Contemporary DTADs are not able to implement such a reduction in the number of refresh cycles.
To implement this principle aspect of the invention, a new address decoder is used which defines and address word differently than that of conventional address decoders used in current DTADs.
The address decoder of the present invention uses a consecutive number of least significant bits of the address word to define a column address of the memory location to be accessed; a consecutive number of least significant bits following the column address to define the specific DRAM to be selected; and a consecutive number of most significant bits to define the row address of the specific memory location to be accessed.
This new architecture results in the accessing of memory locations in the manner described above, namely, that the lowest rows of every DRAM within the memory structure are accessed before a next higher row within the structure is accessed