Test-facilitating circuit for information processing devices

DETAILED DESCRIPTION Therefore, it is an object of the present invention to provide a test-facilitating circuit for information processing devices, which can be widely used and has a simple construction.
Moreover, it is another object of the present invention to provide a test-facilitating circuit for information processing devices, in which the self-test mode and the failure analysis mode can be suitably selected.
To achieve the above-stated objects, a test-facilitating circuit for information processing devices according to the present invention comprises an operational mode register for indicating an operational mode of an information processing device, a memory in which are contained microinstructions necessary for carrying out a first and a second test mode, a test data generating circuit for generating a test data necessary for the first test mode, a gate which is connected to the test data generating circuit and the operational mode register, and transfers a test data from the test data generating circuit to an internal bus in accordance with the microinstruction when the operational mode register designates the first test mode, and always prohibits the test data transfer from the test data generating circuit to the internal bus irrespectively of the microinstruction when the operational mode register designates the second test mode, an external-test-data-inputting circuit which is operatively connected to the internal bus and an external input terminal of the information processing device, and prohibits data transfer from the external input terminal to the internal bus when the operational mode register designates the first test mode, and transfers a test data given to the external input terminal to the internal bus in accordance with the microinstruction designating the test data transfer from the test data generating circuit to the internal bus when the operational mode register designates the second test mode, and a test-result-outputting circuit which is operatively connected to the internal bus and an external output terminal of the information processing device, and transfers a data on the internal bus to the external output terminal when the operational mode register designates either the first or the second test mode