 Data output buffer of a semiconducter memory device |
| It is therefore object of the present invention to provide a semiconductor memory device capable of ... |
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| Synchronous DRAM having a high data transfer rate |
| Accordingly, it is an object of the present invention to provide a semiconductor memory which has ... |
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| High-speed synchronous write control scheme |
| A semiconductor memory device having pairs of data lines for reading and writing data signals to ... |
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| Elasticity buffer for data/clock synchronization |
| OF PREFERRED EMBODIMENT The present invention has application to any data transfer system that ... |
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| Computer systems and methods for pipelined transfer of data between modules |
| Synchronous Global Bus The chief object of the present invention is to perform fast block transfers ... |
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| Dynamic random access memory system |
| It is object of the present invention to minimize the number of address control pins and signal ... |
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| Optical clock distribution system |
| OF THE PREFERRED EMBODIMENT In the following detailed description of the preferred embodiment, ... |
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| Modular bus with single or double parallel termination |
| Single Channel Bus In one embodiment of a modular single channel bus architecture, a master bus ... |
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| Memory controller with low skew control signal |
| OF THE PREFERRED EMBODIMENTS Prior to discussing the preferred embodiments of the invention, a ... |
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Token-based serialisation of instructions in a multiprocessor system
| Details |
Inventors: Pfeffer, Erwin; Getzlaff, Klaus-Joerg; Gaertner, Ute; Tast, Hans-Werner;
Assignee: International Business Machines Corporation (Armonk, NY)
Primary Examiner: Treat; William M.
Assistant Examiner:
Attorney, Agent or Firm: Ehrlich; Marc A.
A process is disclosed to serialize instructions that are to be processed serially in a multiprocessor system, with the use of a token, where the token can be assigned on request to one of the processors, which thereupon has the right to execute the command. If the command consists of dristibuted tasks, the token remains blocked until the last dependent task belonging to the command has also been executed. It is only then that the token can be assigned to another instruction. Moreover, a device is described to manage this token, which features three states: a first state, in which the token is available, a second state, in which the token is assigned to one of the processors, and a third state, in which the token is blocked, because dependent tasks still have to be carried out. Moreover, a circuit is disclosed with which the token principle that is introduced can be implemented in a simple manner. The token is only available if none of the processors i is in possession of the token and if no dependent task is pending at any of the processors. The OR chaining of signals to form a signal C which is set if the token is not available represents the basic circuitry with which the serialisation of commands consisting of distributed tasks is carried out. The invention is applied particularly in the case of commands such as IPTE (invalidate page-table entry) and SSKE (set storage key extended), which modify the address translation tables in the memory that are used in common by all processors. |
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DETAILED DESCRIPTION It is the task of the invention to provide a process for the serialisation of instructions in a multiprocessor system.
In this case, the need to serialise specified commands arises from the fact that these commands modify a resource which is common to all processors.
It is the particular task of the invention to provide a suitable serialisation process for the execution of commands which consist of one initial task to be executed on the initiating processor, and tasks dependent upon this initial task which are to be executed on the other processors.
The execution of dependent tasks may be necessary if local copies of the joint resource have to be updated.
It is the further task of the invention to minimise the waiting period which comes into being during the execution of the various tasks, in order to guarantee high performance.
It is also important to ensure the data integrity during the execution of commands which consist of distributed tasks.
It is the particular task of the invention to propose an improved type of execution specifically for the command to invalidate a page-table entry, IPTE, and for the command to modify the key information relating to a page, SSKE.
It is also intended to disclose a device to manage the token with which the proposed serialisation process can be carried out.
Furthermore, it is the task of the invention to implement this device with a low outlay on hardware.
According to the invention, the task is accomplished by means of a device to manage a token for the serialisation of instructions which are to be processed serially in a multiprocessor system, where a processor can only execute the instructions which are to be processed serially if it is in possession of a token, and the device to manage the token features the following states: a first state, in which the token is not assigned to any of the processors, and the token can be assigned to a processor which requests the token; a second state, in which the token is assigned to one of the processors, and the token cannot be assigned to a processor which requests the token; and a third state, in which the token is not assigned to any of the processors, and the token cannot be assigned to a processor which requests the token
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I/O Systems 
